Abstract
In a digital verification system, multipliers play a crucial role. In practice, multipliers are grouped in to unsigned and signed types. An unsigned multiplier performs the multiplication of two unsigned binary numbers, whereas in signed multiplier, the multiplication is performed by each bit of binary numbers. It may be extended within its range or a valid result. In the literature, number of approaches has been reported that defines signed multiplication such as Booth, Array multiplier, Wallace tree, and Baugh-Wooley. They suggested high-speed signed multiplication algorithms. However, there is a scope of improvising the performance delay, power, and speed in the signed multiplier. In this paper, we design a signed multiplier using “Urdhva Tiryagbhyam” (UT) sutra. The proposed design presents an architecture that is used to multiply unsigned decimal number to signed binary number. With the use of the UT sutra, the proposed signed binary multipliers design helps in reducing the area, while the system performance is improvised. The suggested design is synthesized using ISE Xilinx 14.5 and implemented using different field programmable gate array (FPGA) devices. For validation, the proposed design is compared with the previously reported architectures. From the results, the superiority of the suggested design is claimed.
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Behera, N., Pradhan, M., Mishro, P.K. (2023). Analysis of Delay in 16 × 16 Signed Binary Multiplier. In: Yadav, R.P., Nanda, S.J., Rana, P.S., Lim, MH. (eds) Proceedings of the International Conference on Paradigms of Computing, Communication and Data Sciences. Algorithms for Intelligent Systems. Springer, Singapore. https://doi.org/10.1007/978-981-19-8742-7_13
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DOI: https://doi.org/10.1007/978-981-19-8742-7_13
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