Abstract
In this survey, the comparison results of current mode logic styles such as MOS Current Mode Logic (MCML), Dynamic Current Mode Logic (DyCML), and Positive Feedback Source Coupled Logic (PFSCL) gate structures are analyzed. In this, MCML and PFSCL are static logic circuits. The dynamic logic uses a clock signal as one of the inputs. The simulation results are performed at a voltage of 1 V and a temperature of 27 °C. The values of power, propagation delay, and power delay product are obtained and analyzed using the Cadence Virtuoso tool. The power and the delay values are verified with Monte Carlo simulations using a histogram plot of 200 samples. The process variations for different corners are simulated and the parametric analysis with different temperatures are compared for the different topologies of current mode logic gates. From the comparison, it is clear that Dynamic CML provides high performance and operates in a low-power environment.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Allstot DSC, Kiaei S, Shristawa M (1993) Folded source-coupled logic vs. CMOS static logic for low-noise mixed-signal ICs. IEEE Trans Circuits Sys 40:553–563. https://doi.org/10.1109/81.244904
Kup BMJ, Dijkmans EC, Naus PJA, Sneep J (1991) A bit-stream digital-to-analog converter with 18-b resolution. IEEE J Solid-State Circuits 26(12):1757–1763. https://doi.org/10.1109/4.104166
Yu J, Dai FF (2010) A 3-dimensional Vernier ring time-to-digital converter in 0.13µm CMOS. In: IEEE custom integrated circuits conference 2010, pp 1–4. https://doi.org/10.1109/CICC.2010.561743
Kiaei S, Chee SH, Allstot D (1990) CMOS source-coupled logic for mixed-mode VLSI. In: IEEE International symposium on circuits and systems, vol 2, pp 1608–1611. https://doi.org/10.1109/ISCAS.1990.112444
Caruso G, Macchiarella A (2008) Optimum design of two-level MCML gates. In: 2008 15th IEEE international conference on electronics, circuits and systems, pp 141–144. https://doi.org/10.1109/ICECS.2008.4674811
Musicer JM, Rabaey J (2000) MOS current mode logic for low power, low noise, CORDIC computation in mixed-signal environments. In: Proceedings of the 2000 international symposium of low power electronics and design, pp 102–107. https://doi.org/10.1145/344166.344532
Allam MW, Elmasry MI (2000) Dynamic current mode logic (DyCML), a new low-power high-performance logic family. In: Proceedings of the IEEE 2000 custom integrated circuits conference (Cat. No. 00CH37044), pp 421–424. https://doi.org/10.1109/CICC.2000.852699
Allam MW, Elmasry MI (2001) Dynamic current mode logic (DyCML): a new low-power high-performance logic style. IEEE J Solid-State Circuits 36(3):550–558. https://doi.org/10.1109/4.910495
Alioto M, Pancioni L, Rocchi S, Vignoli V (2004) Modeling and evaluation of positive-feedback source-coupled logic. IEEE Trans Circuits Syst I Regul Pap 51(12):2345–2355. https://doi.org/10.1109/TCSI.2004.838149
Alioto M, Pancioni L, Rocchi S, Vignoli V (2007) Power–delay–area–noise margin tradeoffs in positive-feedback MOS current-mode logic. IEEE Trans Circuits Syst I Regul Pap 54(9):1916–1928. https://doi.org/10.1109/TCSI.2007.904685
Gupta K, Pandey N, Gupta M (2020) Model and design of improved current mode logic gates. Springer, Singapore. https://doi.org/10.1007/978-981-15-0982-7
Gupta K, Sridhar R, Chaudhary J, Pandey N, Gupta M (2011) Performance comparison of MCML and PFSCL gates in 0.18 μm CMOS technology. In: 2nd International conference on computer and communication technology (ICCCT-2011), pp 230–233. https://doi.org/10.1109/ICCCT.2011.6075165
Hassan H, Anis M, Elmasry M (2005) MOS current-mode circuits: analysis, design, and variability. IEEE Trans Very Large Scale Integr (VLSI) Syst 13(8):885–898. https://doi.org/10.1109/TVLSI.2005.853609
Alioto M, Palumbo G (2005) Model and design of bipolar and MOS current-mode logic: CML, ECL and SCL digital circuits. Kluwer Academic Publications
Rabaey JM, Chandrakasan A, Nikolic B (2003) Digital integrated circuits, 2nd edn. Pearson Education
Bansal M, Singh H, Sharma G (2021) A taxonomical review of multiplexer designs for electronic circuits and devices. J Electron Inf 02:77–88
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2023 The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Sivasakthi, M., Radhika, P. (2023). Performance Comparison of MCML, PFSCL, and Dynamic CML Gates with Parametric Analysis in 45 nm CMOS Technology. In: Bindhu, V., Tavares, J.M.R.S., Vuppalapati, C. (eds) Proceedings of Fourth International Conference on Communication, Computing and Electronics Systems . Lecture Notes in Electrical Engineering, vol 977. Springer, Singapore. https://doi.org/10.1007/978-981-19-7753-4_35
Download citation
DOI: https://doi.org/10.1007/978-981-19-7753-4_35
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-19-7752-7
Online ISBN: 978-981-19-7753-4
eBook Packages: EngineeringEngineering (R0)