Abstract
Filters are an integral part of Digital Signal Processors (DSPs), which are necessary for signal processing in digital devices. DSPs are required to process sound signals to provide meaningful data and they are also required to process images captured by digital cameras. Multipliers and adders together form most parts of a filter. Existing filter architectures utilize various multipliers like Array multiplier, Wallace multiplier, Vedic multiplier, etc. These multipliers have a high delay resulting in performance degradation of the filters. Thus, an improvement in the architecture of the multiplier results in the betterment of the overall performance of the filters. The multipliers in turn can be improved by making changes in the algorithm used for the reduction of partial products and also by making changes to the architecture of the adder. For this purpose, a modified Dadda multiplier in which the final addition is done using the Kogge-Stone adder is being proposed in this work. The designed multiplier is an 8-bit multiplier that takes in 9-bit signed magnitude values as input and gives out 23-bit outputs which are then added together for the output to be produced. The FIR and IIR systems have been designed using VHDL and implemented in Vivado 2017.4 to obtain results.
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References
Mittal A, Nandi A, Yadav D (2017) Comparative study of 16-order FIR filter design using different multiplication techniques. IET Circuits Devices Syst 11(3):196–200
Ykuntam Yd, Pavani K, Saladi K (2020) Design and analysis of High speed Wallace tree multiplier using parallel prefix adders for VLSI circuit designs. In: 2020 11th international conference on computing, communication and networking technologies (ICCCNT), pp 1–6. https://doi.org/10.1109/ICCCNT49239.2020.9225404
Raju A, Patnaik R, Babu RK, Mahato P (2016) Parallel prefix adders—a comparative study for fastest response. In: 2016 international conference on communication and electronics systems (ICCES), pp 1–6. https://doi.org/10.1109/CESYS.2016.7889974
Prasath AM, Arjun RV, Deepaknath K, Gayathree K (2020) Implementation of optimized digital filter using Sklansky adder and Kogge stone adder. In: 2020 6th international conference on advanced computing and communication systems (ICACCS), pp 661–664. https://doi.org/10.1109/ICACCS48705.2020.9074440
Aboagye AK. Overflow avoidance techniques in cascaded IIR filter ...—ti.com [online]. Available at: https://www.ti.com/lit/pdf/spra509
Sayed JF, Hasan BH, Muntasir B, Hasan M, Arifin F (2021) Design and evaluation of a FIR filter using hybrid adders and Vedic multipliers. In: 2021 2nd international conference on robotics, electrical and signal processing techniques (ICREST), pp 748–752. https://doi.org/10.1109/ICREST51555.2021.9331063
AlJuffri AA et al (2015) ASIC realization and performance evaluation of scalable microprogrammed FIR filters using Wallace tree and Vedic multipliers. In: 2015 IEEE 15th international conference on environment and electrical engineering (EEEIC), pp 1995–1998. https://doi.org/10.1109/EEEIC.2015.7165480
Gaur N, Kapur S, Mehra A (2020) Application of Vedic multiplier: design of a FIR filter. In: 2020 4th international conference on electronics, communication and aerospace technology (ICECA), pp 234–237. https://doi.org/10.1109/ICECA49313.2020.9297659
Malviya KK, Nandi A (2018) Design of IIR filter using Wallace tree multiplier. In: 2018 2nd international conference on power, energy and environment: towards smart technology (ICEPE), pp 1–4. https://doi.org/10.1109/EPETSG.2018.8659159
Thakur AS, Tiwari V (2018) Design high speed FIR filter based on complex Vedic multiplier using CBL adder. In: 2018 international conference on recent innovations in electrical, electronics & communication engineering (ICRIEECE), pp 559–563. https://doi.org/10.1109/ICRIEECE44171.2018.9008438
Maurya KAK, Lakshmanna YR, Sindhuri KB, Kumar NU (2017) Design and implementation of 32-bit adders using various full adders. In: 2017 innovations in power and advanced computing technologies (i-PACT), pp 1–6. https://doi.org/10.1109/IPACT.2017.8245176
Devika C, Anita JP (2022) Design of a high-speed binary counter using a stacking circuit. Inventive communication and computational technologies. Springer, Singapore, pp 135–143
Ghayathri T, Lavanya T, Srivastava Y, Anita JP (2021) Optimization of EOR and ENOR for design of full adders with efficient transistor sizing. In: 2021 5th international conference on trends in electronics and informatics (ICOEI). IEEE, pp 107–112
Mohan N, Aravinda Kumar M, Dhanush D, Gokul Prasath J, Kumar JS (2021) Low transition dual LFSR for low power testing. Inventive communication and computational technologies. Springer, Singapore, pp 397–406
Reddy BM, Ramesh SR (2021) Design of combinational arithmetic circuits using quantum dot cellular automata. In: 2021 5th international conference on trends in electronics and informatics (ICOEI). IEEE, pp 117–122
Karuppusamy P (2019) Design and analysis of low-power. High-speed Baugh Wooley multiplier. J Electron 1(02):60–70
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Yadeeswaran, K.S., Prakalya, D., Mithun Mithra, N., Athukuri, C., Mohan, N. (2023). FIR and IIR Filter Design Using Modified Dadda Multiplier. In: Bindhu, V., Tavares, J.M.R.S., Vuppalapati, C. (eds) Proceedings of Fourth International Conference on Communication, Computing and Electronics Systems . Lecture Notes in Electrical Engineering, vol 977. Springer, Singapore. https://doi.org/10.1007/978-981-19-7753-4_15
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DOI: https://doi.org/10.1007/978-981-19-7753-4_15
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