Abstract
Floating point numbers provide more range as compared to the fixed point values. The multiplier is one of the main blocks of a processor. For improved performance, there is a need for fast and efficient floating point multipliers. The single electron transistor (SET) is a prominent advanced device structure for achieving high-end computing system. This paper describes the implementation of single precision floating point multiplier using SET (single electron transistor) for better performance. Design and simulation of floating point multiplier have been performed using Cadence Virtuoso. In this paper, we are comparing SET-based floating point multiplier with 16 nm CMOS and then power and delay had been compared. The main objective of this paper is to reduce power consumption and increase the speed or reduce the delay of execution. IEEE 754 standard has been used to represent floating point numbers. Here, floating point multiplier is implemented and verified using the Cadence Virtuoso tool. Thus, SET-based floating point multiplier provides better execution in lowering the power and increasing the speed.
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Banik, S., Trivedi, R., Kalavadiya, A., Agrawal, Y., Parekh, R. (2023). A Single Electron Transistor-Based Floating Point Multiplier Realization at Room Temperature Operation. In: Dhavse, R., Kumar, V., Monteleone, S. (eds) Emerging Technology Trends in Electronics, Communication and Networking. Lecture Notes in Electrical Engineering, vol 952. Springer, Singapore. https://doi.org/10.1007/978-981-19-6737-5_4
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DOI: https://doi.org/10.1007/978-981-19-6737-5_4
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