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Design of an All Digital Phase-Locked Loop Using Cordic Algorithm

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Advances in Signal Processing and Communication Engineering

Abstract

This paper presents a design of an all digital phase-locked loop (ADPLL) using Cordic Algorithm. In an ADPLL all the components are digital in nature. ADPLL are being used in a lot of different applications specially in the communication. The ADPLL presented in this paper is built completely using all digital blocks, i.e. Digital phase detector, Digital IIR filter and a digital algorithmic VCO. A CORDIC algorithm-based phase detector and a CORDIC-based VCO is used, which alters its operating frequency depending on the output of the loop filter to lock the output signal with the input signal. The proposed ADPLL model is simulated using Simulink and then the HDL version of the same is simulated using ModelSim. It was found that the proposed system exhibit excellent locking behaviour.

CBIT, Hyderabad, Telangana, India

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References

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Acknowledgements

The Authors would like to thank the CBIT. We would also like to thank D. Shanthi Priya and K. Suhethaa for their support.

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Correspondence to Mohd Ziauddin Jahangir .

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© 2022 The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

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Jahangir, M.Z., Paidimarry, C.S., Sikander, M., Shravanthi, M.V. (2022). Design of an All Digital Phase-Locked Loop Using Cordic Algorithm. In: Kumar Jain, P., Nath Singh, Y., Gollapalli, R.P., Singh, S.P. (eds) Advances in Signal Processing and Communication Engineering. Lecture Notes in Electrical Engineering, vol 929. Springer, Singapore. https://doi.org/10.1007/978-981-19-5550-1_14

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