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Intelligent Sustainable Systems pp 29–41Cite as

Implementation of Classical Error Control Codes for Memory Storage Systems Using VERILOG

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Part of the book series: Lecture Notes in Networks and Systems ((LNNS,volume 458))

Abstract

Error coding is a method of detecting and correcting errors that ensures the detection of information bits and error recovery in case of damage. Encoding is done using mathematical techniques that pad extra bits to data which aid the recovery of the original message. Several error coding techniques offering different error rates and recovery capabilities are employed in modern-day communication systems facilitating error-free transmission of information bits. Hardware-based implementations of these error coding techniques for robust memory systems and processors has become imperative due to error resistance compared to their software counterparts. In this work, the authors demonstrate the VERILOG implementation targeted for Artix-7 board, various error coding, and correction methodologies in the view of hardware storage using field programmable gate array (FPGA), thereby providing the readers an insight into the performance and advantages offered by these techniques. Their performance in terms of power consumption and utilization is evaluated and analyzed.

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Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore, India

    Sreevatsan Radhakrishnan, Syed Ishtiyaq Ahmed & S. R. Ramesh

Authors
  1. Sreevatsan Radhakrishnan
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  2. Syed Ishtiyaq Ahmed
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  3. S. R. Ramesh
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Corresponding author

Correspondence to S. R. Ramesh .

Editor information

Editors and Affiliations

  1. Gnanmani College of Engineering and Technology, Namakkal, India

    Jennifer S. Raj

  2. Department of Computer Science, Kennesaw State University, Kennesaw, GA, USA

    Yong Shi

  3. Faculty of Communication Sciences, University of Teramo, Teramo, Italy

    Danilo Pelusi

  4. Automatics and Applied Software, Aurel Vlaicu University of Arad, Arad, Romania

    Valentina Emilia Balas

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Radhakrishnan, S., Ishtiyaq Ahmed, S., Ramesh, S.R. (2022). Implementation of Classical Error Control Codes for Memory Storage Systems Using VERILOG. In: Raj, J.S., Shi, Y., Pelusi, D., Balas, V.E. (eds) Intelligent Sustainable Systems. Lecture Notes in Networks and Systems, vol 458. Springer, Singapore. https://doi.org/10.1007/978-981-19-2894-9_3

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