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Beyond-Silicon Computing: Nano-Technologies, Nano-Design, and Nano-Systems

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Emerging Computing: From Devices to Systems

Part of the book series: Computer Architecture and Design Methodologies ((CADM))

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Abstract

For decades, humankind has enjoyed the energy efficiency benefits of scaling transistors smaller and smaller, but these benefits are waning. In a worldwide effort to continue improving computing performance, many researchers are exploring a wide range of technology alternatives, ranging from new physics (spin-, magnetic-, tunneling-, and photonic-based devices) to new nanomaterials (carbon nanotubes, two-dimensional materials, superconductors) to new devices (non-volatile embedded memories, ferroelectric-based logic and memories, q-bits) to new systems, architectures, and integration techniques (advanced die- and wafer-stacking, monolithic three-dimensional (3D) integration, on-chip photonic interconnects). However, developing new technologies from the ground up is no simple task, and requires an end-to-end approach addressing many challenges along the way. First of all, a detailed analysis of the overall potential benefits of a new technology is essential; it can take years to bring a new technology to the level of maturity required for high-volume production, and so a team of researchers must ensure upfront that they are developing the right technologies for the right applications. For example, many emerging nanotechnologies are subject to nano-scale imperfections and variations in material properties—how does one overcome these challenges at a very-large scale? Will new design techniques be required? Will circuit and system designers even use the same approaches to designing next generation systems, or would an entirely different approach offer much better results? What level of investment will be required to develop these new technologies, designs, and systems, and at the end of the day, will the outcome be worth the effort? These are just examples of the some of the major questions that are essential to consider as early as possible.

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References

  • M.M.S. Aly et al., Energy-efficient abundant-data computing: the N3XT 1,000 x. IEEE Comput. 48(12), 24–33 (2015)

    Article  Google Scholar 

  • M.M.S. Aly, T.F. Wu, A. Bartolo, Y.H. Malviya, W. Hwang, G. Hills, I. Markov et al., The N3XT approach to energy-efficient abundant-data computing. Proc. IEEE 107(1), 19–48 (2018)

    Google Scholar 

  • A.G. Amer, R. Ho, G. Hills, A.P. Chandrakasan, M.M. Shulaker, 29.8 SHARC: self-healing analog with RRAM and CNFETs, in 2019 IEEE International Solid-State Circuits Conference-(ISSCC) (IEEE, 2019), pp. 470–472

    Google Scholar 

  • M.S. Arnold, A.A. Green, J.F. Hulvat, S.I. Stupp, M.C. Hersam, Sorting carbon nanotubes by electronic structure using density differentiation. Nat. Nanotechnol. 1(1), 60–65 (2006)

    Article  Google Scholar 

  • J.-L. Baltzinger, B. Delahaye, Semiconductor Technologies, ed. by J. Grym (IntechOpen, 1999), Chap. 4, pp. 57–78

    Google Scholar 

  • M.D. Bishop, G. Hills, T. Srimani, C. Lau, D. Murphy, S. Fuller, J. Humes, A. Ratkovich, M. Nelson, M.M. Shulaker, Fabrication of carbon nanotube field-effect transistors in commercial silicon manufacturing facilities. Nat. Electron. 1–10 (2020)

    Google Scholar 

  • B.H. Calhoun, A.P. Chandrakasan, A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation. IEEE J. Solid-State Circuits 42(3), 680–688 (2007)

    Google Scholar 

  • Q. Cao et al., Arrays of single-walled carbon nanotubes with full surface coverage for high-performance electronics. Nat. Nanotechnol. 8, 180–186 (2013)

    Article  Google Scholar 

  • B. Chava, J. Ryckaert, L. Mattii, S.M.Y. Sherazi, P. Debacker, A. Spessot, D. Verkest, DTCO exploration for efficient standard cell power rails, in Design-Process-Technology Co-optimization for Manufacturability XII. International Society for Optics and Photonics, vol. 10588 (2018), p. 105880B

    Google Scholar 

  • L.T. Clark, V. Vashishtha, L. Shifren, A. Gujja, S. Sinha, B. Cline, C. Ramamurthy, G. Yeric, ASAP7: a 7-nm finFET predictive process design kit. Microelectron. J. 53, 105–115 (2016)

    Google Scholar 

  • J. Ding et al., A hybrid enrichment process combining conjugated polymer extraction and silica gel adsorption for high purity semiconducting single-walled carbon nanotubes. Nanoscale 7, 15741–15747 (2015)

    Article  Google Scholar 

  • D.J. Frank, Y. Taur, H.-S. Philip Wong, Generalized scale length for two-dimensional effects in MOSFETs. IEEE Electron Device Lett. 19(10), 385–387 (1998)

    Google Scholar 

  • L. Gomez, I. Aberg, J.L. Hoyt, Electron transport in strained-silicon directly on insulator ultrathin-body n-MOSFETs with body thickness ranging from 2 to 25 nm. IEEE Electron Device Lett. 28(4), 285–287 (2007)

    Article  Google Scholar 

  • A.A. Green, M.C. Hersam, Ultracentrifugation of single-walled nanotubes. Mater. Today 10, 59–60 (2007)

    Article  Google Scholar 

  • P. Hashemi et al., Strained Si1-x Gex-on-insulator PMOS FinFETs with excellent sub-threshold leakage, extremely-high short-channel performance and source injection velocity for 10 nm node and beyond, in Proceedings of the Symposium on VLSI Technology (VLSI-Technology), Digest Technical Papers (2014a), pp. 1–2

    Google Scholar 

  • P. Hashemi et al., First demonstration of high-Ge-content strained- Si1-x Gex(x = 0.5) on insulator PMOS FinFETs with high hole mobility and aggressively scaled fin dimensions and gate lengths for high- performance applications, in Proceedings of the IEEE International Electron Devices Meeting (2014b), pp. 16.1.1–16.1.4

    Google Scholar 

  • G. Hills, J. Zhang, M.M. Shulaker, H. Wei, C.-S. Lee, A. Balasingam, H.-S. Philip Wong, S. Mitra, Rapid co-optimization of processing and circuit design to overcome carbon nanotube variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(7), 1082–1095 (2015)

    Google Scholar 

  • G. Hills, M.G. Bardon, G. Doornbos, D. Yakimets, P. Schuddinck, R. Baert, D. Jang et al. Understanding energy efficiency benefits of carbon nanotube field-effect transistors for digital VLSI. IEEE Trans. Nanotechnol. 17(6), 1259–1269 (2018)

    Google Scholar 

  • G. Hills, C. Lau, A. Wright, S. Fuller, M.D. Bishop, T. Srimani, P. Kanhaiya et al., Modern microprocessor built from complementary carbon nanotube transistors. Nature 572(7771), 595–602 (2019)

    Google Scholar 

  • R. Ho, C. Lau, G. Hills, M.M. Shulaker, Carbon nanotube CMOS analog circuitry. IEEE Trans. Nanotechnol. 18, 845–848 (2019)

    Article  Google Scholar 

  • P.S. Kanhaiya, C. Lau, G. Hills, M. Bishop, M.M. Shulaker, 1 Kbit 6T SRAM arrays in carbon nanotube FET CMOS, in 2019 Symposium on VLSI Technology (IEEE, 2019a), pp. T54–T55

    Google Scholar 

  • P.S. Kanhaiya, C. Lau, G. Hills, M.D. Bishop, M.M. Shulaker, Carbon nanotube-based CMOS SRAM: 1 kbit 6T SRAM arrays and 10T SRAM cells. IEEE Trans. Electron Devices 66(12), 5375–5380 (2019b)

    Google Scholar 

  • K.J. Kuhn, Considerations for ultimate CMOS scaling. IEEE Trans. Electron Devices 59(7), 1813–1828 (2012)

    Article  Google Scholar 

  • C. Lau, T. Srimani, M.D. Bishop, G. Hills, M.M. Shulaker, Tunable n-type doping of carbon nanotubes through engineered atomic layer deposition HfOX films. ACS Nano 12(11), 10924–10931 (2018)

    Article  Google Scholar 

  • C.-S. Lee, E. Pop, A.D. Franklin, W. Haensch, H.-S. Philip Wong, A compact virtual-source model for carbon nanotube FETs in the sub-10-nm regime—Part I: Intrinsic elements. IEEE Trans. Electron Devices 62(9), 3061–3069 (2015)

    Google Scholar 

  • N. Loubet et al., Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET, in Proceedings of the Symposium on VLSI Technology (2017), pp. T230–T231

    Google Scholar 

  • H. Mertens et al., Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates, in Proceedings of the IEEE Symposium on VLSI Technology (2016), pp. 1–2

    Google Scholar 

  • OpenSPARC (Dec. 2011), http://www.opensparc.net/opensparc-t2

  • N. Patil, A. Lin, J. Zhang, H. Wei, K. Anderson, H.-S. Philip Wong, S. Mitra, VMR: VLSI-compatible metallic carbon nanotube removal for imperfection-immune cascaded multi-stage digital logic circuits using carbon nanotube FETs, in 2009 IEEE International Electron Devices Meeting (IEDM) (IEEE, 2009), pp. 1–4

    Google Scholar 

  • C. Qiu, Z. Zhang, M. Xiao, Y. Yang, D. Zhong, L.-M. Peng, Scaling carbon nanotube complementary transistors to 5-nm gate lengths. Science 355(6322), 271–276 (2017)

    Article  Google Scholar 

  • Y. Sasaki et al., Novel junction design for NMOS Si Bulk-FinFETs with extension doping by PEALD phosphorus doped silicate glass, in Proceedings of the IEEE International Electron Devices Meeting (2015), pp. 21–28

    Google Scholar 

  • M.M. Shulaker, G. Hills, N. Patil, H. Wei, H.-Y. Chen, H.-S. Philip Wong, S. Mitra. Carbon nanotube computer. Nature 501(7468), 526–530 (2013a)

    Google Scholar 

  • M.M. Shulaker, J.V. Rethy, G. Hills, H. Wei, H.-Y. Chen, G. Gielen, H.-S. Philip Wong, S. Mitra, Sensor-to-digital interface built entirely with carbon nanotube FETs. IEEE J. Solid-State Circuits 49(1), 190–201 (2013b)

    Google Scholar 

  • M.M. Shulaker, K. Saraswat, H.-S. Philip Wong, S. Mitra. Monolithic three-dimensional integration of carbon nanotube FETs with silicon CMOS, in 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers (IEEE, 2014), pp. 1–2

    Google Scholar 

  • M.M. Shulaker, G. Hills, T.F. Wu, Z. Bao, H.-S. Philip Wong, S. Mitra. Efficient metallic carbon nanotube removal for highly-scaled technologies, in 2015 IEEE International Electron Devices Meeting (IEDM) (IEEE, 2015), pp. 32–34

    Google Scholar 

  • M.M. Shulaker, G. Hills, R.S. Park, R.T. Howe, K. Saraswat, H.-S. Philip Wong, S. Mitra. Three- dimensional integration of nanotechnologies for computing and data storage on a single chip. Nature 547(7661), 74–78 (2017)

    Google Scholar 

  • T. Srimani, G. Hills, C. Lau, M. Shulaker, Monolithic three-dimensional imaging system: carbon nanotube computing circuitry integrated directly over silicon imager, in 2019 Symposium on VLSI Technology (IEEE, 2019), pp. T24–T25

    Google Scholar 

  • T. Srimani et al., Heterogeneous integration of BEOL logic and memory in a commercial foundry: multi-tier complementary carbon nanotube logic and resistive RAM at a 130 nm node, in VLSI (2020)

    Google Scholar 

  • S.D. Suk et al., Investigation of nanowire size dependency on TSNWFET, in Proceedings of the IEEE International Electron Devices Meeting (2007), pp. 891–894

    Google Scholar 

  • K. Uchida, J. Koga, S.-I. Takagi, Experimental study on carrier transport mechanisms in double-and single-gate ultrathin-body MOSFETs-Coulomb scattering, volume inversion, and/spl TSOI-induced scattering, in Proceedings of the IEEE International Electron Devices Meeting Technical Digest (2003), pp. 33–35

    Google Scholar 

  • T.F. Wu, H. Li, P.-C. Huang, A. Rahimi, G. Hills, B. Hodson, W. Hwang et al., Hyperdimensional computing exploiting carbon nanotube FETs, resistive RAM, and their monolithic 3D integration. IEEE J. Solid-State Circuits 53(11), 3183–3196 (2018)

    Google Scholar 

  • T.F. Wu, B.Q. Le, R. Radway, A. Bartolo, W. Hwang, S. Jeong, H. Li et al., 14.3 A 43 pJ/cycle non-volatile microcontroller with 4.7 ÎĽs shutdown/wake-up integrating 2.3-bit/cell resistive RAM and resilience techniques, in 2019 IEEE International Solid-State Circuits Conference-(ISSCC) (IEEE, 2019), pp. 226–228

    Google Scholar 

  • J. Zhang, N.P. Patil, S. Mitra, Probabilistic analysis and design of metallic-carbon-nanotube-tolerant digital logic circuits. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 28(9), 1307–1320 (2009)

    Google Scholar 

  • J. Zhang, N. Patil, H.-S. Philip Wong, S. Mitra, Overcoming car- bon nanotube variations through co-optimized technology and circuit design, in Proceedings of the InternationalElectron Devices Meeting (IEDM), Washington, DC, USA, 2011, pp. 4.6.1–4.6.4

    Google Scholar 

  • D. Zhong, M. Xiao, Z. Zhang, L.M. Peng, Solution-processed carbon nanotubes based transistors with current density of 1.7 mA/ÎĽm and peak transconductance of 0.8 mS/ÎĽm, in Proceedings of the 2017 IEEE International Electron Devices Meeting (IEDM) (IEEE, 2017), pp. 5–6

    Google Scholar 

  • X. Zhou, J.-Y. Park, S. Huang, J. Liu, P.L. McEuen, Band structure, phonon scattering, and the performance limit of single-walled carbon nanotube transistors. Phys. Rev. Lett. 95(14) (2005), Art. no. 146805

    Google Scholar 

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Hills, G. (2023). Beyond-Silicon Computing: Nano-Technologies, Nano-Design, and Nano-Systems. In: Aly, M.M.S., Chattopadhyay, A. (eds) Emerging Computing: From Devices to Systems. Computer Architecture and Design Methodologies. Springer, Singapore. https://doi.org/10.1007/978-981-16-7487-7_2

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  • DOI: https://doi.org/10.1007/978-981-16-7487-7_2

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