Abstract
Central processing unit (CPU) is the brain of the computer, and arithmetic and logic unit (ALU) serves as the major component of the CPU. In ALU, for the addition of multiple bits, ripple carry adder (RCA) with carry select adder (CSA) configuration is used in this paper. These configurations require various blocks of full adders in cascaded form leading to enhanced area of the circuit. Therefore, this paper mainly focuses on reducing the area of such adders, so that implementation of ALU can be done in minimum space. Here, the area of 4-bit and 8-bit adders with CSA is designed and optimized in such a way that adders can improve the area consumption. The designing of the proposed adder is implemented in Verilog hardware description language (HDL) and simulated using ISIM simulator. It is synthesized and implemented using Xilinx ISE 14.7 by selecting Spartan 3E family and XC3S100E as the device. The proposed 4-bit adder and 8-bit adder reduces the area by 16.8 and 7.38%, respectively.
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Zade, A., Singha, S.K., Talukdar, J., Prathima, A., Mummaneni, K. (2022). Implementation of Arithmetic Logic Unit Using Area-Efficient Adder. In: Das, K.N., Das, D., Ray, A.K., Suganthan, P.N. (eds) Proceedings of the International Conference on Computational Intelligence and Sustainable Technologies. Algorithms for Intelligent Systems. Springer, Singapore. https://doi.org/10.1007/978-981-16-6893-7_5
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DOI: https://doi.org/10.1007/978-981-16-6893-7_5
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