Abstract
Power consumption and speed of computing systems depend on their arithmetic modules such as adder, subtractor, and multiplier. So, the need for high speed, error tolerance, and power efficiency nature of few applications has been improved by developing approximate adders. Increasing the effectiveness of integrated circuits by making the trade-off between accuracy and cost has got significant importance. A systematic methodology for optimizing the architecture of approximate adders has been proposed and called optimized lower part constant-OR adder (LOCA). In this article, the approximate adders are designed by redesigning its logic circuit, implemented on reconfigurable architectures, and then compared with traditional adder architectures. The proposed architecture outperforms its contemporary architectures in terms of hardware and accuracy.
The authors have retracted this article because Figures 1, 2 and 3, Tables 1, 2, 3 and 4, as well as parts of the text, were duplicated from a previously published article by Ayad Dalloo, Ardalan Najafi and Alberto Garcia-Ortiz [1]. Both authors agree to this retraction.
[1] A. Dalloo, A. Najafi and A. Garcia-Ortiz, “Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 8, pp. 1595-1599, Aug. 2018, doi: 10.1109/TVLSI.2018.2822278
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Change history
01 January 2022
Retraction Note to: Chapter “Optimized Lower Part Constant-OR Adder for Multimedia Applications” in: P. Karrupusamy et al. (eds.), Sustainable Communication Networks and Application, Lecture Notes on Data Engineering and Communications Technologies 93, https://doi.org/10.1007/978-981-16-6605-6_19
References
D. Ayad, N. Ardalan, G.O. Alberto, Systematic design of an approximate adder: the optimized lower-part constant-OR adder (2018)
J. Satori, R. Kumar, Stochastic computing. Found. Trends Electron. Design Autom. 5(3), 153–210 (2011)
S. Mittal, A survey of techniques for approximate computing. ACM Comput. Surv. 48(4), 62-1–62-33 (2016)
A.B. Kahng, S. Kang, Accuracy-configurable adder for approximate arithmetic designs, in Proceedings of the 49th Annual Design Automation Conference (DAC) (2012), pp. 820–825
D. Mohapatra, V.K. Chippa, A. Raghunathan, K. Roy, Design of voltage-scalable meta-functions for approximate computing, in Proceedings of the Design, Automation and Test in Europe (2011), pp. 1–6
S. Ajmera, M. Vucha, A. Kokkula, High speed architecture for orthogonal code convolution, in Proceedings of the International Conference on Intelligent Sustainable Systems (ICISS, 2017)
N. Zhu, W.L. Goh, K.S. Yeo, An enhanced low-power high-speed adder for error tolerant application, in Proceedings of the 12th International Symposium Integerates Circuits (2009), pp. 69–72
M. Vucha, A.L. Siridhara, High speed cryptography architecture for health ınformation exchange. Int. J. Adv. Trends Comput. Sci. Eng. 8(4), (2019)
T. Kalyani, S. Monika, B. Naresh, M. Vucha, Accident detection and alert system. Int. J. Innov. Technol. Exploring Eng. (IJITEE) 8(4S2), (2019). ISSN: 2278–3075
S.-L. Lu, Speeding up processing approximate circuits, Computer 37(3), L 67–73, (2004)
T. Anuradha, K.A. Manjusha, R. Karthik, M. Vucha, A.L. Siridhara, Design and ımplementation of an audio parser and player. J. Eng. Appl. Sci. 12(20), 5301–5306 (2017)
D. Esposito, D. De Caro, A.G.M. Strollo, variable latency speculative parallel prefix adders for unsigned and signed operands. IEEE Trans. Circuits Syst. I, Reg. Papers 63(8), 1200–1209 (2016)
H. Jiang, J. Han, F. Lombardi, A comparative review and evaluation of approximate adders, in Proceedings of the 25th Edition Great Lakes Symp VLSI (GLSVLSI) (2015), pp. 343–348
A.L. Siridhara, M. Vucha, T. Ravinder, Performance evaluation of parallel multipliers. J. Eng. Appl. Sci. 12, 5186–5189 (2017)
A. Najafi, M. Weiβbrich, G.P. Vaya, A. Garica-Ortiz, A fair comparison of adders in stochastic regime, in Proceedings of the 27th International Symposium Power Timing Modeling, Optim. Simulation(PATMOS) (2017), pp. 1–6
M. Vucha, A. Rajawat, Design and VLSI implementation of systolic array architecture for matrix multiplications. Int. J. Comput. Appl. 26(3), 18–22 (2011)
M. Vucha, L.S. Varghese, Design space exploration of DSP techniques for hardware software co-design: an OFDM transmitter case study. Int. J. Comput. Appl. 116(20), 29–33 (2015)
P. Gurjar, R. Solanki, P. Kanslival, M. Vucha, VLSI ımplementation of adders for high speed ALU. Int. J. Comput. Appl. 29(10), 11–15 (2011)
M.C. Sudeep, M. Sharath Bimba, M. Vucha, Design and FPGA implementation of high speed vedic multiplier. Int. J. Comput. Appl. 116(20), 6–9 (2014)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2022 The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Vucha, M., Siridhara, A.L. (2022). RETRACTED CHAPTER: Optimized Lower Part Constant-OR Adder for Multimedia Applications. In: Karrupusamy, P., Balas, V.E., Shi, Y. (eds) Sustainable Communication Networks and Application. Lecture Notes on Data Engineering and Communications Technologies, vol 93. Springer, Singapore. https://doi.org/10.1007/978-981-16-6605-6_19
Download citation
DOI: https://doi.org/10.1007/978-981-16-6605-6_19
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-16-6604-9
Online ISBN: 978-981-16-6605-6
eBook Packages: EngineeringEngineering (R0)