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Comparative Study of Latch Type and Differential Type Sense Amplifier Circuits Using Power Reduction Techniques

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Microelectronic Devices, Circuits and Systems (ICMDCS 2021)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 1392))

Abstract

A quantitative and yield analysis of different types of sense amplifiers has been done. Furthermore, power reduction techniques such as sleep transistor technique, footer stack technique, sleep stack technique, and sleepy keeper technique also have been done over sense amplifiers. Observations specifically concentrate on the dissipation of power of various combinations of sense amplifiers. The findings of the simulation reveal that the suggested implementation of the sleep transistor technique system in the current mode differential sense amplifier often leads to a drastic decrease, in power dissipation considering 1.2 V power supply voltage.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, GLA University, Mathura, India

    Reeya Agrawal

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  1. Reeya Agrawal
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Correspondence to Reeya Agrawal .

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Editors and Affiliations

  1. Vellore Institute of Technology, Vellore, India

    V. Arunachalam

  2. Vellore Institute of Technology, Vellore, India

    K. Sivasankaran

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Agrawal, R. (2021). Comparative Study of Latch Type and Differential Type Sense Amplifier Circuits Using Power Reduction Techniques. In: Arunachalam, V., Sivasankaran, K. (eds) Microelectronic Devices, Circuits and Systems. ICMDCS 2021. Communications in Computer and Information Science, vol 1392. Springer, Singapore. https://doi.org/10.1007/978-981-16-5048-2_21

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  • DOI: https://doi.org/10.1007/978-981-16-5048-2_21

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-16-5047-5

  • Online ISBN: 978-981-16-5048-2

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