Read–Write Decoupled Single-Ended 9T SRAM Cell for Low Power Embedded Applications

Abstract

Static Random-Access Memory (SRAM) is the most significant building block of embedded Systems and microprocessor. Traditional 6T cell used as a data storage element in the SRAM cell but is suffered from low stability, low process tolerance and high-power consumption issue. Technology is continuously scaling down into the nanometer regime to achieve higher integration. Minimum size cell is used to achieve higher integration density in nm technology node but it significantly increases the leakage current and decreases stability. These issues are more critical in the conventional 6T cell. This article introduces a new read/write decouple single-ended 9T cell with high stability, low process tolerance, and low static and dynamic power consumption. This 9T cell shows higher read/write stability due to read buffer and dynamic loop cutting techniques respectively. Furthermore, it shows the low leakage current due to the stack transistor technique and low dynamic power due to a single bit line (BL). In contrast to the traditional 6T SRAM cell, the proposed 9T cell has a 4.28 × higher Read Static Noise Margin (RSNM), 1.06×  higher Write Static Noise Margin (WSNM), and approximately the same Hold Static Noise Margin (HSNM). The proposed 9T cell reported 0.48× lower power consumption compared to the conventional 6T cell. This 9T cell shows the half select free operation and aids bit interleaving architectures therefore it may be an appealing choice for low power embedded system.