Abstract
The network on chip (NoC) has become a good idea to improve the network communication in multi-core processing structures for the complex chip system (SoC). Unlike the bus-based system, NoC integrates hundreds or thousands of intellectual properties (IP) such as processors, memories, or other custom design on a single chip. The routing technique and topology system selection play a vital role to increase the performance, and the shortest route between the receiver and sender can be estimated by calculating the count of hop routers in a network by applying the suitable routing topology algorithm. Therefore, the network performance is improved, and latency is reduced. We implement the XY routing and weight-based path selection algorithm for 6D torus topology with the Xilinx simulator tool.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Madhubala T, Karthika P, Sobana S (2017)A competent performance estimation of king torus topology. In: International conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC), Palladam, pp 214–217
Madhubala T, Gayathri G, Karthikeyan I (2017)A competent performance analysis of king mesh topology. In: International conference on electrical, instrumentation and communication engineering (ICEICE), Karur, pp 1–5
Upadhyay M, Shah M, Bhanu PV, Soumya J, Cenkeramaddi LR (2019)Multi-application based network-on-chip design for mesh-of-tree topology using global mapping and reconfigurable architecture. In: International conference on VLSI design and international conference on embedded systems (VLSID), Delhi, NCR, India, pp 527–528
Lochana ASR, Arthi K (2017)Over looped 2D mesh topology for network on chip. In: 1st international conference on innovations in information and communication technology (ICIICT), Chennai, India, pp1–5
Phing NY, Warip MNM, Ehkan P, Zulkefli FW, Ahmad RB (2017) Topology design of extended torus and ring for low latency network-on-chip architecture. 15(2):869–876
Bahrebar P, Stroobandt D (2017) Adaptive and reconfigurable bubble routing technique for 2D Torus interconnection networks. In: International symposium on reconfigurable communication-centric systems-on-chip (ReCoSoC), Madrid, pp 1–8
Chemli B, Zitouni A (2017)Architecture and performances comparison of network on chip router for hierarchical mesh topology. In: 2017 international conference on engineering & MIS (ICEMIS), Monastir, pp 1–4
Kullu P, Tosun S (2019) MARM-GA: mapping applications to reconfigurable mesh using genetic algorithm. In: Euromicro conference on digital system design (DSD), Kallithea, Greece, pp 13–18
Kunthara RG, Neethu K, James RK, Sleeba SZ, Jose J (2019) DoLaR: double layer routing for Bufferless mesh network-on-chip. In: TENCON conference (TENCON), Kochi, India, pp 400–405
Khan S, Anjum S, Gulzari UA, Afzal MK, Umer T, Ishmanov F (2018) An efficient algorithm for mapping real time embedded applications on NoC architecture. IEEE Access 6:16324–16335
Priya S, Agarwal S, Kapoor HK (2018) Fault tolerance in network on chip using bypass path establishing packets. In: International conference on VLSI design and international conference on embedded systems (VLSID), Pune, pp 457–458
Pereira LMV, Melo DR, Zeferino CA, Bezerra EA (2018) Analysis of LEON3 systems integration for a network-on-chip. In: Latin-American test symposium (LATS), Sao Paulo, pp 1–3
Chen K, Wang T (2018) NN-Noxim: high-level cycle-accurate NoC-based neural networks simulator. In: International workshop on network on chip architectures (NoCArc), Fukuoka, pp 1–5
Upadhyay M, Shah M, Bhanu PV, Soumya J, Cenkeramaddi LR (2019) Multi-application based network-on-chip design for mesh-of-tree topology using global mapping and reconfigurable architecture. In: International conference on VLSI design and international conference on embedded systems (VLSID), Delhi, NCR, India, pp 527–528
Tsai W-C, Lan Y-C, Hu Y-H, Chen S-J (2012) Networks on chips: structure and design methodologies. Hindawi Publ Corp J Electr Comput Eng 2012. Article ID 509465
Phing NY, Warip MNM, Ehkan P, Zulkefli FW, Ahmad RB (2017) Topology design of extended torus and ring for low latency network-on-chip architecture. TELKOMNIKA 15(2):869–876
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2022 The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Satish, E.G., Ramachandra, A.C. (2022). Comparative Performance Analysis of Routing Topology for NoC Architecture. In: Shetty, N.R., Patnaik, L.M., Nagaraj, H.C., Hamsavath, P.N., Nalini, N. (eds) Emerging Research in Computing, Information, Communication and Applications. Lecture Notes in Electrical Engineering, vol 790. Springer, Singapore. https://doi.org/10.1007/978-981-16-1342-5_34
Download citation
DOI: https://doi.org/10.1007/978-981-16-1342-5_34
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-16-1341-8
Online ISBN: 978-981-16-1342-5
eBook Packages: EngineeringEngineering (R0)