Abstract
Increasing the count of transistors packed within integrated circuits necessitates efficient communication architecture such as Network-on-Chip (NoCs) to deal with scalability, bandwidth, latency, and optimized CPU core utilization goals. To extend the applicability of Moore’s law, multiprocessor architectures have been introduced, which in turn requires a higher level of synchronization and concurrency to enable enhancement in system performance. This research deals with global communication for NoC-multi-core system using the Intelligent Adaptive Arbitration technique to enable task parallelization by showing a perspective for the deployment of Intelligent Adaptive Arbitration on different NoC architecture(s) to enable parallel computing with fair bandwidth distribution and low latency. This research also opens up room for the various network-on-chip topology to constitute a unification of the latest trends of intra-chip communication.
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References
Dumitrescu C, Ciocoi V, Pop M (2006) Power QUICC™ II pro family of communications processors: a broad range of advanced functionality in IP convergence. WSEAS Trans Electron 3(6):330
Kyriakakis E, Ngo K, Öberg J (2017) Implementation of a fault-tolerant, globally-asynchronous-locally-synchronous, inter-chip NoC communication bridge on FPGAs. In: 2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and international symposium of System-on-Chip (SoC)
Tutsch D, Hommel G (2008) MLMIN: a multi-core processor and parallel computer network topology for multicast. Comput Oper Res 35(12):3807–3821
Ebrahimi M, et al (2012) HARAQ: congestion-aware learning model for highly adaptive routing algorithm in on-chip networks. In: 2012 IEEE/ACM sixth international symposium on networks-on-chip
Gray J (2016) Grvi phalanx: a massively parallel risc-v fpga accelerator. In: 2016 IEEE 24th annual international symposium on Field-Programmable Custom Computing Machines (FCCM)
Shieh W-Y, Pong C-C (2013) Energy and transition-aware runtime task scheduling for multi-core processors. J Parallel Distrib Comput 73(9):1225–1238
Márquez AL et al (2011) Parallelism on multi-core processors using Parallel, FX. Adv Eng Softw 42(5):259–265
Abadi M et al (2018) A scalable and adaptable hardware NoC-based self organizing map. Microprocess Microsyst 57:1–14
Agarwal A, Iskander C, Shankar R (2009) Survey of network on chip (noc) architectures & contributions. J Eng Comput Architect 3(1):21–27
Zitouni A, Tourki R (2008) Arbiter synthesis approach for SoC multiprocessor systems. Comput Electr Eng 34(1):63–77
Abid N et al (2013) A modular and generic router TLM model for speedup network-on-chip topology generation. In: 10th international multi-conferences on Systems, Signals & Devices (SSD13)
Babu YA, Prasad G, Solomon JB (2018) Design of low-power and high-performance network interface for 2 × 2 SDM-based NoC and implementation on spartan 6 FPGA. In: Progress in advanced computing and intelligent engineering. Springer, pp 545–551
Andión JM et al (2013) A novel compiler support for automatic parallelization on multi-core systems. Parallel Comput 39(9):442–460
Chen C-H, Lee G-W, Huang J-D, Jou J-Y (2006) A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication. In: Asia and South Pacific conference on design automation: IEEE, pp 600–605
Loucif S (2013) Performance evaluation of hierarchical-torus NoC. In: 2013 27th international conference on advanced information networking and applications workshops: IEEE
Hu J-h, Zhang S-w (2011) NoC architecture with local bus design for network coding. In: 2011 6th international ICST conference on communications and networking in China (CHINACOM): IEEE
El-Moursy MA, Ismail M (2008) High throughput high performance NoC switch. In: 2008 NORCHIP: IEEE
Kunthara RG, James RK (2019) Performance comparison of asynchronous NoC router architectures. In: International conference on computer networks and communication technologies, Springer
Attia S et al (2018) Optimizing FPGA-based hard networks-on-chip by minimizing and sharing resources. Integration 63:138–147
Dielissen J, Radulescu A, Goossens K, Rijpkema E (2003) Concepts and implementation of the phillips network-on-chip. In: Proceedings of IP based SOC (IPSOC): IFIP
Pestana SG et al (2004) Cost-performance trade-offs in networks on chip: a simulation-based approach. In: Design, automation and test in Europe conference and exhibition, 2004: Proceedings
Goossens K (2005) Formal methods for networks on chips. In: Fifth international conference on application of concurrency to system design, 2005. ACSD 2005
Kumar S et al (2002) A network on chip architecture and design methodology. In: Proceedings of IEEE computer society annual symposium on VLSI, 2002
Mahadevan TBS (2006) A survey of research and practices of network-on-chip. ACM Comput Surv (CSUR) 38(1):50–51
Jantsch A, Lauter R, Vitkowski A (2005) Power analysis of link level and end-to-end data protection in networks on chip. In: IEEE international symposium on circuits and systems, ISCAS 2005
Babu YA, Prasad G (2018) Performance analysis and implementation of highly reconfigurable modified SDM-Based NoC for MPSoC platform on Spartan6 FPGA. In: Progress in intelligent computing techniques: theory, practice, and applications, Springer, pp 441–449
Guerrier P, Greiner A (2000) A generic architecture for on-chip packet-switched interconnections. In: Proceedings on design, automation and test in Europe conference and exhibition 2000
Andriahantenaina A, Greiner A (2003) Micro-network for SoC: implementation of a 32-port SPIN network. In: Design, automation and test in Europe conference and exhibition
Pandey K, Gaikwad MA (2018) Review of different topologies for Noc architecture using NS2
Leiserson CE (1985) Fat-trees: universal networks for hardware-efficient supercomputing. IEEE Trans Comput C-34(10):892–901
Yao Y, Lu Z (2018) iNPG: accelerating critical section access with in-network packet generation for NoC based many-cores. In: 2018 IEEE international symposium on high performance computer architecture (HPCA). IEEE
Felicijan T, Bainbridge J, Furber S (2003) An asynchronous low latency arbiter for Quality of Service (QoS) applications. In: Microelectronics, 2003. ICM 2003. Proceedings of the 15th international conference
Bjerregaard T (2005) The MANGO clockless network-on-chip:Concepts and implementation. In: Informatics and mathematical modeling. 2005, Technical University of Denmark: Lyngby
Bjerregaard T, Mahadevan S, Olsen RG, Sparsø J (2004) A channel library for asynchronous circuit design supporting mixed-mode modeling. In: Proceedings of the 14th international workshop on power and timing modeling, optimization and simulation (PATMOS)
Dall’Osso M, et al (2003) Xpipes: a latency insensitive parameterized network-on-chip architecture for multiprocessor SoCs. In: Computer design, 2003. Proceedings. 21st international conference (2003)
Bertozzi D, et al (2005) NoC synthesis flow for customized domain specific multiprocessor systems-on-chip. Parallel Distrib Syst IEEE Trans 16(2):113–129
Akhtar MN, Sidek O (2013) An intelligent adaptive arbiter for maximum CPU utilization, fair bandwidth allocation and low latency. IETE J Res 59(1):48–54
McCalpin JD (1995) Memory bandwidth and machine balance in current high performance computers. IEEE Comput Soc Tech Committee Comput Archit (TCCA) Newsletter 2(19–25) (1995)
Akhtar MN, Mohamad-Saleh J, Sidek O (2015) Design and simulation of a parallel adaptive arbiter for maximum CPU utilization using multi-core processors. Comput Electr Eng 47:51–68
Akhtar MN, Saleh JM, Awais H, Bakar EA (2020) Map- Reduce based tipping point scheduler for parallel image processing. Expert Syst Appl 139
Acknowledgements
This research is supported by the School of Aerospace Engineering, Universiti Sains Malaysia using the RUI Grant 1001/PAERO/8014035; RU Top Down Grant 1001/PAERO/870052 and Institute of Post Graduate Studies (IPS) under USM Fellowship and School of Electrical and Electronics Engineering (EEE).
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Akhtar, M.N., Azam, Q., Almohamad, T.A., Mohamad-Saleh, J., Bakar, E.A., Janvekar, A.A. (2021). An Overview of Multi-Core Network-on-Chip System to Enable Task Parallelization Using Intelligent Adaptive Arbitration. In: Bahari, M.S., Harun, A., Zainal Abidin, Z., Hamidon, R., Zakaria, S. (eds) Intelligent Manufacturing and Mechatronics. Lecture Notes in Mechanical Engineering. Springer, Singapore. https://doi.org/10.1007/978-981-16-0866-7_2
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DOI: https://doi.org/10.1007/978-981-16-0866-7_2
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