Abstract
A fixed point divider is needed for determining the result of division up to a fixed number of points in its fractional part. The divider does so with a good accuracy so that the result can be used for further applications, where the accuracy as well as speed of different modules should be high. This paper presents a 32-bit fixed point divider design based on Newton Raphson division algorithm. The design comprises of two units viz., one is reciprocal unit and the other is the multiplication unit. For the reciprocal unit the divider uses Newton Raphson method and for multiplication unit it uses the multiplication operator. The Verilog HDL coding of the proposed divider design is simulated using Xilinx Vivado tool and synthesized using Cadence EDA tool.
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Acknowledgements
The technical support through SMDP-C2SD project awarded to NIT Hamirpur by MeitY (Ministry of Electronics and Information Technology), Government of India, New Delhi, is duly acknowledged.
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Pandey, P.K., Singh, D., Chandel, R. (2021). Fixed-Point Divider Using Newton Raphson Division Algorithm. In: Nath, V., Mandal, J.K. (eds) Proceeding of Fifth International Conference on Microelectronics, Computing and Communication Systems. Lecture Notes in Electrical Engineering, vol 748. Springer, Singapore. https://doi.org/10.1007/978-981-16-0275-7_19
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DOI: https://doi.org/10.1007/978-981-16-0275-7_19
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