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TSU: A Two-Stage Update Approach for Persistent Skiplist

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Advanced Computer Architecture (ACA 2020)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 1256))

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Abstract

Skiplist, a widely used in-memory index structure, could incur crash inconsistency when running on emerging NVRAM (Non-Volatile Random Access Memory). Logging or strict serialization can ensure crash consistency at the cost of severe performance degradation. In this paper, we propose TSU, a Two-stage update approach to improve the performance of persistent skiplist while preserve crash consistency. TSU exploits space locality of skiplist and atomic write of NVRAM, thus effectively reducing expensive cache line flush (clflush) operations. To this end, we category all four crash inconsistent states into two types: recoverable and unrecoverable. TSU could guarantee the crash state is recoverable by constraining the memory access order for insertion and deletion. We further design a persistency algorithm to reduce clflush by preserving the memory persistent order of skiplist update. In addition, we develop a concurrent search for TSU. The evaluation result shows that TSU can reduce cache line flush with up to 47.6%, and decrease the average request latency by up to 36% for insertions compared to the strict serialization.

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References

  1. Bhandari, K., Chakrabarti, D.R., Boehm, H.J.: Makalu: fast recoverable allocation of non-volatile memory. In: ACM SIGPLAN Notices, vol. 51, pp. 677–694. ACM (2016)

    Google Scholar 

  2. Chen, Q., Yeom, H.: Design of skiplist based key-value store on non-volatile memory. In: 2018 IEEE 3rd International Workshops on Foundations and Applications of Self* Systems (FAS* W), pp. 44–50. IEEE (2018)

    Google Scholar 

  3. Chen, S., Jin, Q.: Persistent B+-trees in non-volatile main memory. Proc. VLDB Endow. 8(7), 786–797 (2015)

    Article  Google Scholar 

  4. Cooper, B.F., Silberstein, A., Tam, E., Ramakrishnan, R., Sears, R.: Benchmarking cloud serving systems with YCSB. In: Proceedings of the 1st ACM Symposium on Cloud Computing, pp. 143–154. ACM (2010)

    Google Scholar 

  5. Fomitchev, M., Ruppert, E.: Lock-free linked lists and skip lists. In: Proceedings of the Twenty-Third Annual ACM Symposium on Principles of Distributed Computing, pp. 50–59. ACM (2004)

    Google Scholar 

  6. George, L.: HBase: The Definitive Guide: Random Access to Your Planet-Size Data. O’Reilly Media, Inc., Sebastopol (2011)

    Google Scholar 

  7. Ghemawat, S., Dean, J.: LevelDB (2011)

    Google Scholar 

  8. Herlihy, M.: A methodology for implementing highly concurrent data objects. ACM Trans. Program. Lang. Syst. (TOPLAS) 15(5), 745–770 (1993)

    Article  Google Scholar 

  9. Huai, Y., et al.: Spin-transfer torque MRAM (STT-MRAM): challenges and prospects. AAPPS Bull. 18(6), 33–40 (2008)

    Google Scholar 

  10. Hwang, D., Kim, W.H., Won, Y., Nam, B.: Endurable transient inconsistency in byte-addressable persistent B+-tree. In: 16th USENIX Conference on File and Storage Technologies. (FAST 2018), Oakland, CA, pp. 187–200. USENIX Association (2018)

    Google Scholar 

  11. Kaiyrakhmet, O., Lee, S., Nam, B., Noh, S.H., Choi, Y.: SLM-DB: single-level key-value store with persistent memory. In: 17th USENIX Conference on File and Storage Technologies, (FAST 2019), Boston, MA, pp. 191–205. USENIX Association (2019)

    Google Scholar 

  12. Kannan, S., Bhat, N., Gavrilovska, A., Arpaci-Dusseau, A., Arpaci-Dusseau, R.: Redesigning LSMS for nonvolatile memory with NoveLSM. In: 2018 \(\{\)USENIX\(\}\) Annual Technical Conference (\(\{\)USENIX\(\}\)\(\{\)ATC\(\}\) 2018), pp. 993–1005 (2018)

    Google Scholar 

  13. Lakshman, A., Malik, P.: Cassandra: a decentralized structured storage system. ACM SIGOPS Oper. Syst. Rev. 44(2), 35–40 (2010)

    Article  Google Scholar 

  14. Oukid, I., Lasperas, J., Nica, A., Willhalm, T., Lehner, W.: FPTree: a hybrid SCM-DRAM persistent and concurrent B-tree for storage class memory. In: International Conference on Management of Data (2016)

    Google Scholar 

  15. Packard, H.: Understanding the Intel/Micron 3D Xpoint Memory (2015)

    Google Scholar 

  16. Ping, C., Lee, W.C., Yuan, X.: Making B+-tree efficient in PCM-based main memory (2014)

    Google Scholar 

  17. Pugh, W.: Skip lists: a probabilistic alternative to balanced trees. Commun. ACM 33(6), 668–677 (1990)

    Article  Google Scholar 

  18. Rao, D.S., et al.: System software for persistent memory. In: Bulterman, D.C.A., Bos, H., Rowstron, A.I.T., Druschel, P. (eds.) Ninth Eurosys Conference 2014, (EuroSys 2014), Amsterdam, The Netherlands, 13–16 April 2014, pp. 15:1–15:15. ACM (2014)

    Google Scholar 

  19. Rixner, S., Dally, W.J., Kapasi, U.J., Mattson, P., Owens, J.D.: Memory access scheduling. ACM SIGARCH Comput. Archit. News 28(2), 128–138 (2000)

    Article  Google Scholar 

  20. Seo, J., Kim, W., Baek, W., Nam, B., Noh, S.H.: Failure-atomic slotted paging for persistent memory. In: Chen, Y., Temam, O., Carter, J. (eds.) Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, (ASPLOS 2017), Xi’an, China, 8–12 April 2017, pp. 91–104. ACM (2017)

    Google Scholar 

  21. Shamgunov, N.: The MemSQL in-memory database system. In: IMDM VLDB (2014)

    Google Scholar 

  22. Venkataraman, S., Tolia, N., Ranganathan, P., Campbell, R.H.: Consistent and durable data structures for non-volatile byte-addressable memory. In: USENIX Conference on File and Storage Technologies (2010)

    Google Scholar 

  23. Volos, H., Magalhaes, G., Cherkasova, L., Li, J.: Quartz: a lightweight performance emulator for persistent memory software. In: Proceedings of the 16th Annual Middleware Conference, pp. 37–49. ACM (2015)

    Google Scholar 

  24. Volos, H., Tack, A.J., Swift, M.M.: Mnemosyne: lightweight persistent memory. In: ACM SIGARCH Computer Architecture News, vol. 39, pp. 91–104. ACM (2011)

    Google Scholar 

  25. Wang, Y., et al.: Robustness in the salus scalable block store. In: Proceedings of the 10th USENIX Symposium on Networked Systems Design and Implementation, (NSDI 2013), Lombard, IL, USA, 2–5 April 2013, pp. 357–370. USENIX Association (2013)

    Google Scholar 

  26. Wong, H.S.P., et al.: Phase change memory. Proc. IEEE 98(12), 2201–2227 (2010)

    Article  Google Scholar 

  27. Yang, J., Wei, Q., Cheng, C., Wang, C., Leong, K., He, B.: NV-tree: reducing consistency cost for NVM-based single level systems. In: USENIX Conference on File and Storage Technologies (2015)

    Google Scholar 

  28. Zhou, X., Shou, L., Chen, K., Hu, W., Chen, G.: DPTree: differential indexing for persistent memory. Proc. VLDB Endow. 13(4), 421–434 (2019)

    Article  Google Scholar 

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Acknowledgment

This work is supported in part by National key research and development program of China under Grant 2018YFA0701804 and Grant 2018YFA0701805, in part by the Creative Research Group Project of NSFC No. 61821003.

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Authors and Affiliations

  1. Wuhan National Laboratory for Optoelectronics, Key Laboratory of Information Storage System, Engineering Research Center of Data Storage Systems and Technology, School of Computer Science and Technology, Huazhong University of Science and Technology, Ministry of Education of China, Wuhan, China

    Shucheng Wang & Qiang Cao

Authors
  1. Shucheng Wang
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  2. Qiang Cao
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Corresponding author

Correspondence to Qiang Cao .

Editor information

Editors and Affiliations

  1. National University of Defense Technology, Changsha, China

    Dezun Dong

  2. Nankai University, Tianjin, China

    Xiaoli Gong

  3. National University of Defense Technology, Changsha, China

    Cunlu Li

  4. National University of Defense Technology, Changsha, China

    Dongsheng Li

  5. National University of Defense Technology, Changsha, China

    Junjie Wu

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Wang, S., Cao, Q. (2020). TSU: A Two-Stage Update Approach for Persistent Skiplist. In: Dong, D., Gong, X., Li, C., Li, D., Wu, J. (eds) Advanced Computer Architecture. ACA 2020. Communications in Computer and Information Science, vol 1256. Springer, Singapore. https://doi.org/10.1007/978-981-15-8135-9_12

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  • DOI: https://doi.org/10.1007/978-981-15-8135-9_12

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-15-8134-2

  • Online ISBN: 978-981-15-8135-9

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