Abstract
The Low Density Parity Check (LDPC) codes are linear block codes, which are Shannon Limit codes. These codes are attained least error floors of data bits for data transfer applications used in communication systems. However, the proposed LDPC codes are more beneficial than Turbo codes because of reduction in the decoding complexity and detection of the errors in less cycle time. This results the reduction of decoding time, low decoding latency and as well as least error floors in communication, when the transmitted data contains multiple error bits. This paper is proposed to represent the majority logic decoding/detecting of LDPC codes. This paper proposes the Generation of Generator and Parity Check matrices for both Binary and Non-Binary LDPC Codes. Here, the proposed Majority Logic Decoder/Detector (MLDD) is Hard decision decrypting scheme and it uses majority logic decoding based on the data transmission and reception in communication channel. This paper also elaborates the effective implementation of encoding and decoding of LDPC Codes.
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Chinna Babu, J., Mallikharjuna Rao, N. (2021). Throughput Comparison of Majority Logic Decoder/Detector with Other Decoders Used in Communication Systems. In: Kumar, A., Mozar, S. (eds) ICCCE 2020. Lecture Notes in Electrical Engineering, vol 698. Springer, Singapore. https://doi.org/10.1007/978-981-15-7961-5_47
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DOI: https://doi.org/10.1007/978-981-15-7961-5_47
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