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Circuit Design for Non-volatile Magnetic Memory

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Emerging Non-volatile Memory Technologies
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Abstract

High performance low power memory is a topmost requirement in advanced computing systems. Magnetic memory has been considered as a promising solution because of its performance and non-volatility. However, it has various design challenges such as small tunneling magnetoresistance (TMR) ratios and large variability that need to be tackled for reliable operation. This chapter will discuss those challenges and introduce state-of-the-art write and read techniques.

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References

  1. S. Yu, P.-Y. Chen, Emerging memory technologies. IEEE Solid-State Circuits Mag. 8(2), 43–56 (2016)

    Article  Google Scholar 

  2. X. Fong, Y. Kim, S.H. Choday, K. Roy, Failure mitigation techniques for 1T-1MTJ spin-transfer torque MRAM Bit-cells. IEEE Trans. VLSI Syst. 22(2), 384–395 (2012) (Write techs. study)

    Google Scholar 

  3. T.W. Andre, J.J. Nahas, C.K. Subramanian, B.J. Garni, H.S. Lin, A. Omair, W.L. Martino, A 4-Mb 0.18-µm 1T1MTJ Toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers. IEEE J. Solid-State Circuits 40(1), 301–309, (2005) (3-input sensing and unidirectional write drivers)

    Google Scholar 

  4. D. Gogl, C. Arndt, J.C. Barwin, A. Bette, J. DeBrosse, E. Gow, H. Hoenigschmid, S. Lammers, M. Lamorey, Y. Lu, T. Maffitt, K. Maloney, W. Obermaier, A. Sturm, H. Viehmann, D. Willmott, M. Wood, W.J. Gallagher, G. Mueller, A.R. Sitaram, A 16-Mb MRAM featuring bootstrapped. IEEE J. Solid-State Circuits 40(4), 902–908 (2005) (Boostrapped write driver)

    Google Scholar 

  5. X. Bi, Z. Sun, H. Li, W. Wu, Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches, in Proceedings of IEEE/ACM ICCAD, pp. 88–94 (2012) (VOW)

    Google Scholar 

  6. J. Park, T. Zheng, M. Erez, M. Orshansky, Variation-tolerant write completion circuit for variable-energy write STT-RAM architecture. IEEE Trans. VLSI Syst. 24(4), 1351–1360 (2016) (write completion, VEW)

    Google Scholar 

  7. R. Bishnoi, F. Oboril, M. Ebrahimi, M.B. Tahoori, Self-timed read and write operations in STT-MRAM. IEEE Trans. VLSI Syst. 24(5), 1783–1793 (2016) (Self-timed write)

    Google Scholar 

  8. R. Patel, X. Guo, Q. Guo, E. Ipek, E.G. Friedman, Reducing switching latency and energy in STT-MRAM caches with field-assisted writing. IEEE Trans. VLSI Syst. 24(1), 129–138 (2016) (Field-assisted writing)

    Google Scholar 

  9. T. Andre, S. Tehrani, J. Slaughter, N. Rizzo, Structures and methods for a field-reset spin-torque MRAM, U.S. Patent 8 228 715, Jul. 24, 2012

    Google Scholar 

  10. Y. Ding, Method and system for using a pulsed field to assist spin transfer induced switching of magnetic memory elements, U.S. Patent 7 502 249, Mar. 10, 2009

    Google Scholar 

  11. X. Wang et al., Magnetic field assisted STRAM cells, U.S. Patent 8 400 825, Mar. 19, 2013

    Google Scholar 

  12. J.J. Nahas, T.W. Andre, B. Garni, C. Subramanian, H. Lin, S.M. Alam, K. Papworth, W.L. Martino, A 180 Kbit Embeddable MRAM Memory Module. IEEE J. Solid-State Circuits 43(8), 1826–1834 (2007) (selective write)

    Google Scholar 

  13. C.-Y. Chen, S.-H. Wang, C.-W. Wu, Write current self-configuration scheme for MRAM yield improvement. IEEE Trans. VLSI Syst. 21(1), 1260–1270 (2012) (Write current self-config.)

    Google Scholar 

  14. M. Durlam, P.J. Naji, A. Omair, M. De Herrera, J. Calder, J.M. Slaughter, B.N. Engel, N.D. Rizzo, G. Grynkewich, B. Butcher, C. Tracy, K. Smith, K.W. Kyler, J. Jack Ren, J.A. Molla, W.A. Feil, R.G. Williams, S. Tehrani, A 1-Mbit MRAM based on 1T1MTJ Bit cell integrated with copper interconnects. IEEE J. Solid-State Circuits 38(5), 769–773 (2003) (Midpoint ref gen)

    Google Scholar 

  15. G. Jeong, W. Cho, S. Ahn, H. Jeong, G. Koh, Y. Hwang, K. Kim, A 0.24-µm 2.0-V 1T1MTJ 16-kb nonvolatile magnetoresistance RAM with self-reference sensing scheme. IEEE J. Solid-State Circuits 38(11), 1906–1910 (2003) (Self-reference)

    Google Scholar 

  16. M.B. Leslie, R.J. Baker, Noise-shaping sense amplifier for MRAM cross-point arrays. IEEE J. Solid-State Circuits 41(3), 699–704 (2006) (noise shaping and self-referencing)

    Google Scholar 

  17. Y. Chen, H. Li, X. Wang, W. Zhu, W. Xu, T. Zhang, A 130 nm 1.2 V/3.3 V 16 Kb spin-transfer torque random access memory with nondestructive self-reference sensing scheme. IEEE J. Solid-State Circuits 47(2), 560–573 (2012) (Self-reference)

    Google Scholar 

  18. J. De Brosse, D. Gogl, A. Bette, H. Hoenigschmid, R. Robertazzi, C. Arndt, D. Braun, D. Casarotto, R. Havreluk, S. Lammers, W. Obermaier, W.R. Reohr, H. Viehmann, W.J. Gallagher, G. Müller, A high-speed 128-kb MRAM core for future universal memory applications. IEEE J. Solid-State Circuits 39(4), 678–683 (2004) (Symmetrical archi)

    Google Scholar 

  19. J. Kim, K. Ryu, S.H. Kang, S.-O. Jung, A novel sensing circuit for deep submicron spin transfer torque MRAM (STT-MRAM). IEEE Trans. VLSI Syst. 20(1), 181–186 (2012) (Iref-sensing)

    Google Scholar 

  20. J. Kim, K. Ryu, J.P. Kim, S.H. Kang, S.-O. Jung, STT-MRAM sensing circuit with self-body biasing in deep submicron technologies. IEEE Trans. VLSI Syst. 22(7), 1630–1634 (2014). (sensing with body bias)

    Google Scholar 

  21. T. Sugibayashi, N. Sakimura, T. Honda, K. Nagahara, K. Tsuji, H. Numata, S. Miura, K. Shimura, Y. Kato, S. Saito, Y. Fukumoto, H. Honjo, T. Suzuki, K. Suemitsu, T. Mukai, K. Mori, R. Nebashi, S. Fukami, N. Ohshima, H. Hada, N. Ishiwata, N. Kasai, S. Tahara, A 16-Mb Toggle MRAM with burst modes. IEEE J. Solid-State Circuits 42(11), 2378–2385 (2007) (preamp)

    Google Scholar 

  22. T. Na, J. Kim, B. Song, J.P. Kim, S.H. Kang, S.-O. Jung, An offset-tolerant dual-reference-voltage sensing scheme for deep submicrometer STT-RAM. IEEE Trans. VLSI Syst. 24(4), 1361–1370 (2016) (Dual ref volt sensing)

    Google Scholar 

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Correspondence to Tony Tae-Hyoung Kim .

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Kim, T.TH. (2021). Circuit Design for Non-volatile Magnetic Memory. In: Lew, W.S., Lim, G.J., Dananjaya, P.A. (eds) Emerging Non-volatile Memory Technologies. Springer, Singapore. https://doi.org/10.1007/978-981-15-6912-8_6

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