Abstract
Discrete cosine transformation (DCT) is one of an efficient tool which facilitates compression of speech and image signals. This paper focuses on FPGA implementation of discrete cosine transform (DCT-II) which is valid for \( N = 2^{r} \), where N is the length of input sequence and \( r > 1 \). The architecture used is recursive in nature and implemented with reduced hardware complexity. The structure is designed using Verilog Hardware Description Language (HDL) and Zybo Zynq-7000 Development FPGA board is used for implementation. The design utilized \( 7.91\% \) LUTs, \( 6\% \) IOB, \( 32.5\% \) DSPs, and \( 1.43\% \) Flip flops and takes 26 clock cycles to compute all the output coefficients of DCT.
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Jain, R., Jain, P. (2021). FPGA Implementation of Recursive Algorithm of DCT. In: Bansal, P., Tushir, M., Balas, V., Srivastava, R. (eds) Proceedings of International Conference on Artificial Intelligence and Applications. Advances in Intelligent Systems and Computing, vol 1164. Springer, Singapore. https://doi.org/10.1007/978-981-15-4992-2_20
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DOI: https://doi.org/10.1007/978-981-15-4992-2_20
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