Skip to main content
SpringerLink
Log in

Synthesis and Analysis of Optimal Order Butterworth Filter for Denoising ECG Signal on FPGA

  • Conference paper
  • First Online:
Information Management and Machine Intelligence (ICIMMI 2019)

Part of the book series: Algorithms for Intelligent Systems ((AIS))

Abstract

This paper focuses on the synthesis of the design of optimal order Butterworth filter for denoising ECG signal on Field Programmable Gate Array platform. A summary of its resource utilization, the timing and power consumed are presented after synthesis and simulation. This is achieved by conversion of MATLAB code of designed digital filter into Verilog code using the HDL command-line interface. Spartan-6 FPGA (XC6SLX75T with 3FGG676 package) is used as a target device. Xilinx Power Estimator 14.1 tool used to estimate power consumed by digital design. Further, the complexity of the filter structure is also determined on the FPGA platform for its suitability of a hardware efficient filter design. The results suggest that the FPGA based Butterworth filter design for denoising ECG signal reduces the complexity and cost by reducing the number of multipliers and adders, which occupy a small portion of the chip area and consume low power than in MATLAB, hence are suitable for ECG portable device.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 299.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 379.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 379.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Thakur, R., & Khare, K. (2013). High speed FPGA Implementation of FIR Filter For DSP Application. International Journal of Modeling and Optimization, 3(1), 92–94

    Google Scholar 

  2. Kolawole, E. S., Ali, W. H., Cofie, P., Fuller, J., Tolliver, C., & Obiomon, P. (2015). Design and Implementation of low-pass, high- pass and band- pass finite impulse response (FIR) filters using FPGA. Circuit and System, 6, 30–48.

    Google Scholar 

  3. Narsale, R. M., Gawali, D., & Kulkarni, A. (2014). FPGA based design and implementation of low power FIR filter for ECG signal processing. International Journal of Science, Engineering and Technology Research, 3(6), 1673–1678.

    Google Scholar 

  4. Bokde, P. R., & Choudhari, N. K. (2015). Implementation of digital filter on FPGA For ECG signal processing. International Journal of Emerging Technology and Innovative Engineering, 1(2), 175–181.

    Google Scholar 

  5. Dixit, H. V., & Gupta, V. (2012). IIR filters using system generator For FPGA implementation. International Journal of Engineering Research and Applications, 2(5), 303–306.

    Google Scholar 

  6. Kansal, M., Saini, H. S., & Arora, D. (2011). Designing and FPGA implementation of IIR filter used for detecting clinical information from ECG. International Journal of Engineering and Advanced Technology, 1(1), 67–72.

    Google Scholar 

  7. Yadav, S. K., & Mehra, R. (2014). Analysis of FPGA based recursive filter using optimization techniques for high throughput. International Journal of Engineering and Advanced Technology, 3(4), 341–343. ISSN: 2249-8958.

    Google Scholar 

  8. Chou, C. J., Mohanakrishnan, S., & Joseph, B. (1993). FPGA implementation of digital filters. In Evans, Proceeding ICSPAT “93.

    Google Scholar 

  9. Gaikwad, P. K. (2013). FPGA based hardware level analysis of inverse sinc filters. International Journal of Computer Science and Mobile Applications, 1(3), 35–39.

    Google Scholar 

  10. Kumar, P. R., & Meduri, M. (2013). The implementation of high order matched fir filter with distributed arithmetic. International Journal of VLSI and Embedded Systems, 4, 673–676. Article 12196.

    Google Scholar 

  11. Vijaya, V., Baradwaj, V., & Guggilla, J. (2012). Low power FPGA implementation of real-time QRS detection algorithm. International Journal of Science, Engineering and Technology research, 1(5), 140–144.

    Google Scholar 

  12. Ravikumar, M. (2012). Electrocardiogram signal processing on FPGA for emerging healthcare applications. International Journal of Electronics Signals and Systems, 1(3), 91–96.

    Google Scholar 

  13. Xilinx Synthesis and Simulation Design Guide UG626 (v 14.4) December 18, 2012.

    Google Scholar 

  14. Xilinx XPower Estimator User GuideUG440 (v13.4) January 18, 2012.

    Google Scholar 

  15. Bhogeshwar, S. S., Soni, M. K., & Bansal, D. (2016). Study of structural complexity of optimal order digital filters for de-noising ECG Signal. International Journal of Biomedical Engineering and Technology, INDERSCIENCE, in press.

    Google Scholar 

  16. Xilinx Spartan-6 FPGA Data Sheet DS162 (v3.1.1) January 30, 2015.

    Google Scholar 

  17. Xilinx Spartan-6 Family Overview, DS160 (v2.0) October 25, 2011.

    Google Scholar 

  18. Xilinx Spartan-6 FPGA DSP48A1 Slice User Guide UG389 (v1.2) May 29, 2014.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. ECE Department, IIMT College of Engineering, Greater Noida, India

    Seema Nayak

  2. ECE Department, GL Bajaj Institute of Technology and Management, Greater Noida, India

    Amrita Rai

Authors
  1. Seema Nayak
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Amrita Rai
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Seema Nayak .

Editor information

Editors and Affiliations

  1. Poornima Institute of Engineering and Technology, Jaipur, Rajasthan, India

    Dinesh Goyal

  2. Department of Automatics and Applied Informatics, Aurel Vlaicu University of Arad, Arad, Romania

    Valentina Emilia Bălaş

  3. CISCO Technologies, Milpitas, CA, USA

    Abhishek Mukherjee

  4. Universidade de Fortaleza, Fortaleza, Brazil

    Victor Hugo C. de Albuquerque

  5. Poornima Institute of Engineering and Technology, Jaipur, Rajasthan, India

    Amit Kumar Gupta

Rights and permissions

Reprints and permissions

Copyright information

© 2021 Springer Nature Singapore Pte Ltd.

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Nayak, S., Rai, A. (2021). Synthesis and Analysis of Optimal Order Butterworth Filter for Denoising ECG Signal on FPGA. In: Goyal, D., Bălaş, V.E., Mukherjee, A., Hugo C. de Albuquerque, V., Gupta, A.K. (eds) Information Management and Machine Intelligence. ICIMMI 2019. Algorithms for Intelligent Systems. Springer, Singapore. https://doi.org/10.1007/978-981-15-4936-6_39

Download citation

Publish with us

Policies and ethics

Search

Navigation