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On the Hardware Implementation Performance, of Face Recognition Techniques, for Digital Forensics

Conference paper
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Part of the Communications in Computer and Information Science book series (CCIS, volume 1208)

Abstract

As face recognition systems constitute a very useful tool in the sector of Digital Forensics, they should provide accurate and fast results. Although several software implementations for face recognition exist, they are unable to achieve high recognition rate in reasonable time, due to the complex and numerous needed calculations. As a result, there is an on-going research in low-cost hardware implementations, especially based on Field Programmable Gate Arrays (FPGAs), in order to reduce the processing time and the false alarm identification rate. In this work, we introduce the fundamental of algorithms, for face recognition, such as Principal Components Analysis (PCA), and its modified methods, as well as the Local Binary Pattern (LBP). These approaches are applied in different architectures, and alternative FPGA implementations are introduced. We also present implementation synthesis results, based on the recognition time and the allocated hardware resources.

Keywords

Digital forensics Face recognition FPGA Hardware security Cyber security 

Notes

Acknowledgments

This publication is based upon work from COST Action 16101 “MULTI-modal Imaging of FOREnsic SciEnce Evidence” (MULTI-FORESEE), supported by COST (European Cooperation in Science and Technology).

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Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.SCYTALE Group, Computer Engineering and Informatics DepartmentUniversity of PatrasPatrasHellas
  2. 2.University of Donja GoricaPodgoricaMontenegro

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