An Efficient Hardware Architecture for Deblocking Filter in HEVC

Abstract

This paper proposes a new hardware architecture for deblocking filter in a high efficiency video coding (HEVC) system. The proposed hardware is designed by using mixed pipelined and parallel processing architectures. The pixels are processed in the stream of two blocks of $4 \times 32$ samples in which edge filters are applied vertically in a parallel fashion for the processing of luma and chroma samples. These pixels are transposed and reprocessed through the vertical filter for horizontal filtering in a pipelined fashion. Finally, the filtered block will be transposed back to the original direction. The proposed filter is implemented using Verilog HDL, and the design is synthesized using the GPDK 90 nm technology library. Experimental results show that the proposed deblocking filter architecture achieves similar or up to two times higher throughput compared with the existing architectures while occupying a moderate chip area and consuming relatively low logic power. The proposed architecture supports the real-time deblocking filter operation of $4\text {k} \times 2\text {k}$ @60 fps under the clock frequency of 125 MHz with a gate count of 110K.