Abstract
Low power and high speed digital systems are essential for enhancing battery life of portable devices such as smartphones and digital computers. The integral part of any arithmetic and logic unit is adder. When compared to addition, subtraction and multiplication require more hardware resources and processing time. Low power consumption, delay and process variation parameters need to be taken care while designing the integrated circuit. In our proposed work, improved version of Vedic multiplier is designed and implemented by using CSA based on NEDFF. The proposed design offers low power dissipation and high speed. The power and delay results of existing and proposed multipliers are taken by using micro wind tool with technology of 90 nm. The experimental results signify that proposed Vedic multiplier using a CSA based on NEDFF provides 50% improvement in performance.
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References
Gokhale, GR, Bahisonde PD (2015) Design of vedic-multiplier using area-efficient carry select adder. IEEE international conference on advances in computing communication & informatics, pp 576–581
Bhalme LM, Wakpanjar OM., Rakhunde Si (2015) High speed multiplier using vedic mathematics technique. Int J Adv Res Comput Sci Softw Eng 5(2):114–118
Paradhasaradhi D, Anusudha K (2013) An area efficient enhanced SQRT carry select adder. J Eng Res Appl 3(6):876–880
Kumari DP, Rao RSP, Bhaskar BV (2012) A future technology for enhanced operation in flip-flop oriented circuits. Int J Eng Res Appl 2(4):2177–2180
Anitha P, Ramanathan P (2014) Area efficient high speed adder using negative edge triggered D flip flop. Appl Mech Mater 573(187):187–193. https://doi.org/10.4028/www.scientific.net/AMM.573.187
Chauhan R, Alam MZ (2016) Design of 16-bit vedic multiplier using Kogge Stone adder for fast parallel FIR filter. Int J Adv Res Comput Sci Softw Eng 6(5):944–947
Kumar GG, Sahoo SK (2015) Implementation of a high speed multiplier for high-performance and low power applications. In: IEEE conference https://doi.org/10.1109/ISVDAT.2015.7208143. (978-1-4799-1743-3/15)
Edison AJ, Manikandababu CS (2012) An efficient CSLA architecture for VLSI hardware implementation. Int J Manag IT Eng 2(5):610–622
Acknowledgements
I would like to submit my sincere thanks to the management and our beloved Principal Dr. J. Janet, Sri Krishna College of Engineering and Technology, Coimbatore, for providing necessary support and encouragement.
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Anitha, P., Ramanathan, P. (2020). Investigation of Techniques to Recognize Optimal Power Structuring of Vedic Multiplier. In: Jayakumari, J., Karagiannidis, G., Ma, M., Hossain, S. (eds) Advances in Communication Systems and Networks . Lecture Notes in Electrical Engineering, vol 656. Springer, Singapore. https://doi.org/10.1007/978-981-15-3992-3_8
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DOI: https://doi.org/10.1007/978-981-15-3992-3_8
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