Skip to main content

Failure Analysis of Solder Joints

  • Chapter
  • First Online:
Assembly and Reliability of Lead-Free Solder Joints
  • 1394 Accesses

Abstract

As mentioned earlier that reliability of solder joints consists of three major tasks, namely DFR (design for reliability), reliability testing and data analysis, and failure analysis as shown in Fig. 6.1. The reliability testing and data analysis and DFR of lead-free solder joints have been discussed in Chaps. 6 and 7, respectively. Failure analysis is the focus of this chapter.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

eBook
USD 16.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 129.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 179.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Ko K, Cho H (2000) Solder joints inspection using a neural network and fuzzy rule-based classification method. IEEE Trans Electron Packag Manuf 23:93–103

    Google Scholar 

  2. Lau JH, Chu J (2003) 3D X-ray tests and analyses of lead-free PBGA (Plastic Ball Grid Array) package solder joints. Proceedings of SMT International Conference, Chaicago, IL, October 2003, pp J1–13

    Google Scholar 

  3. Laghari M, Memon Q (2015) Identification of faulty BGA solder joint in X-ray images. Int J Future Comput Commun 4:122–125

    Google Scholar 

  4. Wang Z, Liu X, He Z, Su L, Lu X (2019) Intelligent detection of flip chip with the scanning acoustic microscopy and the general regression neural network. Microelectron Eng 217:111–127

    Google Scholar 

  5. Lau JH, Chang C, Lee SW (2000) Failure analysis of solder bumped flip chip on low-cost substrates. IEEE Trans Electron Packag Manuf 23:19–27

    Google Scholar 

  6. Geng P, Bandorawalla T, Cho S, Hsiao H, Kuchy J, Long G, Martinson R, McAllister A, Mello M, Meyyappan K, Williams R, Zhu L (2006) Application of shadow moiré technique to board level manufacturing technologies. IEEE/ECTC Proceedings, May 2006, pp 1816–1820

    Google Scholar 

  7. Thomas J (2012) Projection moiré vs. shadow moiré for warpage measurement and failure analysis of advanced packages. IPC/EXPO, pp 1–4

    Google Scholar 

  8. Ding H, Powell R, Hanna C, Ume C (2003) Warpage measurement comparison using shadow moiré and projection moiré methods. IEEE Trans Comp Pack Technol 25:714–721

    Google Scholar 

  9. Driel W, Zhang G, Janssen J, Ernst L, Su F, Chian K, Yi S (2003) Prediction and verification of process induced warpage of electronic packages. Microelectron Reliab 43:765–774

    Google Scholar 

  10. Lau JH et al (2017) Warpage and thermal characterization of fan-out wafer-level packaging. IEEE Trans CPMT 7:1729–1738

    Google Scholar 

  11. Lau JH, Lee NC et al (2018) Warpage measurements and characterizations of FOWLP with large chips and multiple RDLs. IEEE Trans CPMT 8:1729–1737

    Google Scholar 

  12. JEDEC (2009) Package warpage measurement of surface-mount integrated circuits at elevated temperature. Global Standard for the Microelectronics Industry, Arlington VA, Standard No. JEDEC Standard JESD22-B112A

    Google Scholar 

  13. Lau JH et al (2002) Creep analysis and thermal-fatigue life prediction of the lead-free solder sealing ring of a photonic switch. J Electron Packag 124:403–410

    Google Scholar 

  14. Liu F, Meng G, Zhao M (2010) Experimental investigation on the failure of lead-free solder joints under drop impact. Soldering Surf Mount Technol 22:36–41

    Google Scholar 

  15. Akhtar K, Khan S, Khan S, Asiri A (2018) Scanning electron microscopy: principle and applications in nanomaterials characterization. In: Sharma S (ed) Handbook of materials characterization. New York, Springer

    Google Scholar 

  16. Huang S, Zhan C, Huang Y, Lin Y, Fan C, Chung S, Kao K, Chang J, Wu M, Yang, Lau JH, Chen T (2012) Effects of UBM structure/material on the reliability performance of 3D chip stacking with 30μm-pitch solder micro bump interconnections. IEEE/ECTC Proceedings, May 2012, pp 1287–1292

    Google Scholar 

  17. Lin Y, Zhan C, Juang J, Lau JH, Chen T, Lo R, Kao M, Tian T, Tu K (2011) Electromigration in Ni/Sn intermetallic micro bump joint for 3D IC chip stacking. IEEE/ECTC Proceedings, May 2011, pp 351–357

    Google Scholar 

  18. Wirth R (2009) Focused Ion Beam (FIB) combined with SEM and TEM: advanced analytical tools for studies of chemical composition, microstructure and crystal structure in geomaterials on a nanometre scale. Chem Geol 261:217–229

    Google Scholar 

  19. Ray V (2015) Focused ion beams in failure analysis, design debugging, and security of semiconductor devices. CALCE, University of Maryland, pp 1–35

    Google Scholar 

  20. Yu A, Lau JH, Ho S, Kumar A, Hnin W, Lee W, Jong M, Sekhar V, Kripesh V, Pinjala D, Chen S, Chan C, Chao C, Chiu C, Huang C, Chen C (2011) Fabrication of high aspect ratio TSV and assembly with fine-pitch low-cost solder microbump for Si interposer technology with high-density interconnects. IEEE Trans CPMT 1(9):1336–1344

    Google Scholar 

  21. Yu A, Lau JH, Ho S, Kumar A, Wai Y, Yu D, Jong M, Kripesh V, Pinjala D, Kwong D (2009) Study of 15-μm-pitch solder microbumps for 3D IC integration. IEEE/ECTC Proceedings, May 2009, pp 6–10

    Google Scholar 

  22. Ngo P (1999) Energy dispersive spectroscopy. In: Wagner L (ed) Failure analysis of integrated circuits: tools and techniques. Springer, New York

    Google Scholar 

  23. Zhu J, Shen Y, Zhao S (2016) Chemical analysis of semiconductor devices using TEM energy-dispersive X-ray spectroscopy (EDS) and electron energy-loss spectroscopy (EELS). Proceedings of IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, pp 1–12

    Google Scholar 

  24. Choi W, Yu D, Lee C, Yan L, Yu A, Yoon S, Lau JH, Cho M, Jo Y, Lee H (2008) Development of low temperature bonding using in-based solders. IEEE/ECTC Proceedings, May 2008, pp 1294–1299

    Google Scholar 

  25. Choi W, Premachandran C, Ong C, Xie L, Liao E, Khairyanto A, Ratmin B, Chen K, Thaw P, Lau JH (2009) Development of novel intermetallic joints using thin film indium based solder by low temperature bonding technology for 3D IC stacking. IEEE/ECTC Proceedings, May 2009, pp 333–338

    Google Scholar 

  26. Made R, Gan CL, Yan L, Yu A, Yoon SU, Lau JH, Lee C (2009) Study of low temperature thermocompression bonding in Ag-In solder for packaging applications. J Electron Mater 38:365–371

    Google Scholar 

  27. Yan L-L, Lee C-K, Yu D-Q, Yu A-B, Choi W-K, Lau JH, Yoon S-U (2009) A hermetic seal using composite thin solder In/Sn as intermediate layer and its interdiffusion reaction with Cu. J Electron Mater 38:200–207

    Google Scholar 

  28. Yan LL, Lee V, Yu D, Choi WK, Yu A,Yoon S-U, Lau JH (2008) A hermetic chip to chip bonding at low temperature with Cu/In/Sn/Cu joint. IEEE/ECTC Proceedings, May 2008 pp 1844–1848

    Google Scholar 

  29. Lee C, Yu A, Yan L, Wang H, Han J, Zhang Q, Lau JH (2009) Characterization of intermediate In/Ag layers of low temperature fluxless solder based wafer bonding for MEMS packaging. J Sensor Actuat A Phys 154:85–91

    Google Scholar 

  30. Yu D-Q, Lee C, Yan LL, Choi WK, Yu A, Lau JH (2009) The role of Ni buffer layer on high yield low temperature hermetic wafer bonding using In/Sn/Cu metallization. Appl Phys Lett 94:1–6

    Google Scholar 

  31. Yu DQ, Yan LL, Lee C, Choi WK, Yoon SU, Lau JH (2008) Study on high yield wafer to wafer bonding using In/Sn and Cu metallization. Proceedings of the Eurosensors Conference, pp 1242–1245

    Google Scholar 

  32. Yu D, Lee C, Lau JH (2008) The role of Ni buffer layer between InSn solder and Cu metallization for hermetic wafer bonding. Proceedings of the International Conference on Electronics Materials and Packaging, October 2008, pp 335–338

    Google Scholar 

  33. Yu D, Yan L, Lee C, Choi W, Thew M, Foo C, Lau JH (2008) Wafer level hermetic bonding using Sn/In and Cu/Ti/Au metallization. IEEE/EPTC Proceedings, December 2008, pp 1–6

    Google Scholar 

  34. Chen K, Premachandran C, Choi K, Ong C, Ling X, Khairyanto A, Ratmin B, Myo P, Lau JH (2008) C2W bonding method for MEMS applications. IEEE/EPTC Proceedings, December 2008, pp 1283–1287

    Google Scholar 

  35. Premachandran CS, Lau JH, Ling X, Khairyanto A, Chen K, Pa MEP (2008) A novel, wafer-level stacking method for low-chip yield and non-uniform, chip-size wafers for MEMS and 3D SIP applications. IEEE/ECTC Proceedings, 27–30 May 2008, pp 314–318

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

Copyright information

© 2020 The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Lau, J.H., Lee, NC. (2020). Failure Analysis of Solder Joints. In: Assembly and Reliability of Lead-Free Solder Joints. Springer, Singapore. https://doi.org/10.1007/978-981-15-3920-6_8

Download citation

  • DOI: https://doi.org/10.1007/978-981-15-3920-6_8

  • Published:

  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-15-3919-0

  • Online ISBN: 978-981-15-3920-6

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics