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Implementation of Program Page, Read Page and Block Erase Operations in NAND Flash Memory Controller

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Microelectronics, Electromagnetics and Telecommunications

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 655))

Abstract

In underwater, vehicles like AUV’S, submarines, etc., will travel underwater in hours or days depending on the requirement. The sensors and many subsystems are interfaced in these vehicles. The information from the sensors like direction, voltage and pressure parameter, etc., are collected and stored in the memory. These parameters from the memory and saved into the controlling system. The data is changed from min to min. Earlier NVRAMs used as a memory unit. It is heavy in size and suitable for larger ships and not for smaller in size vehicles. So the unit “NAND flash memory” is being used to store data and as chip. So it is suitable for all types of vehicles. Storage can be done in the form of bytes, pages and block types. “NAND flash memory controller” performs operations like program page, read page and block erase. A VHDL program is developed using a state machine for program page, read page and block erase operations. The simulation of the program and waveforms of program page, read page and block erase operations are using Xilinx software. The complete VHDL program testing is done in FPGA. A Xilinx Spartan-6 FPGA is used to interface the “NAND flash memory controller.”

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References

  1. Yu X, Wang X, Yan W (2014) A high performance solid-state storage system for high speed data acquisition applications. In: IEEE international on electron devices and solid-state circuits (EDSSC), China, pp 1–2

    Google Scholar 

  2. Park C, Talawar P, Won D, Jung MJ, Im JB, Kim S, Choi Y (2006) A high performance controller for NAND flash-based solid state disk (NSSD). In: Proceedings of the 21st IEEE non-volatile semiconductor memory workshop. NVSMW, pp 17–20

    Google Scholar 

  3. Mitiukhina N, Overview of NAND flash high speed interfacing and controller architecture. IEE 5008 memory systems final report 0060805

    Google Scholar 

  4. Micron Technology Inc (2005) The datasheet of Nand flash memory by Micron Technologies. Memory management in NAND flash arrays overview. Technological note TN-29-28

    Google Scholar 

  5. Micron Technology Inc (2009) 64 Gb, 128 Gb, 256 Gb, 512 Gb asynchronous/synchronous NAND features

    Google Scholar 

  6. Kleinfelder SA, The ARIANNA Collaboration (2013) Design and performance of the autonomous data acquisition system for the ARIANNA high energy neutrino detector. IEEE Trans Nucl Sci 60(2):612–618

    Article  Google Scholar 

  7. Kaynak MN, Khayat PR, Parthasarathy S (2017) On die bit error rate estimator for NAND flash memory. IEEE Trans Circuits Syst II 64(7):772–776

    Article  Google Scholar 

  8. Venkata Swathi A, Raju IBK (2017) ASIC implementation of NAND flash memory. Int J Electr Electron Data Commun. ISSN: 2320-2084

    Google Scholar 

  9. Lin CS, Dung LR (2007) A NAND flash memory controller for SD/MMC flash memory card. IEEE Trans Magn 43(2):933–935

    Article  Google Scholar 

  10. Uchigaito H, Miura S, Nito T (2018) Efficient data-allocation scheme for eliminating garbage collection during analysis of big graphs stored in NAND flash memory. IEEE Trans Comput 67(5):646–657

    Article  MathSciNet  Google Scholar 

  11. Rodríguez-Olivares NA, Gómez-Hernández A, Nava-Balanzar L, Jiménez-Hernández H, Soto-Cajiga JA (2018) FPGA-based data storage system on NAND flash memory in RAID 6 architecture for in-line pipeline inspection gauges. IEEE Trans Comput 67(7):1046–1053

    Article  MathSciNet  Google Scholar 

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Correspondence to Ch. Harini .

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Harini, C., Keerthi Priya, B., Rama Koti Reddy, D.V. (2021). Implementation of Program Page, Read Page and Block Erase Operations in NAND Flash Memory Controller. In: Chowdary, P., Chakravarthy, V., Anguera, J., Satapathy, S., Bhateja, V. (eds) Microelectronics, Electromagnetics and Telecommunications. Lecture Notes in Electrical Engineering, vol 655. Springer, Singapore. https://doi.org/10.1007/978-981-15-3828-5_52

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  • DOI: https://doi.org/10.1007/978-981-15-3828-5_52

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-15-3827-8

  • Online ISBN: 978-981-15-3828-5

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