Abstract
The execution of multiplication consumes more time, power and also requires more area than other arithmetic operations. Hence, in floating-point multiplication, performance-optimized mantissa multiplication is necessary to get efficient response. In this paper, unified adder–subtractor-based 24-bit mantissa multiplication is designed. First, single precision floating-point multiplication is designed with Karatsuba algorithm to improve the speed, and later for more better performance, an unified adder–subtractor-based carry-select adder is introduced in Karatsuba algorithm. In this, Karatsuba algorithm is developed by using Vedic multiplication along with unified adder–subtractor logic. Further, the performance metrics are analyzed for the existing techniques with the proposed techniques. All modules are developed with Xilinx ISE.
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Gowreesrinivas, K.V., Samundiswary, P. (2021). Performance Efficient Floating-Point Multiplication Using Unified Adder–Subtractor-Based Karatsuba Algorithm. In: Chowdary, P., Chakravarthy, V., Anguera, J., Satapathy, S., Bhateja, V. (eds) Microelectronics, Electromagnetics and Telecommunications. Lecture Notes in Electrical Engineering, vol 655. Springer, Singapore. https://doi.org/10.1007/978-981-15-3828-5_51
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DOI: https://doi.org/10.1007/978-981-15-3828-5_51
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