Skip to main content
SpringerLink
Log in

FPGA Performance Evaluation of Present Cipher Using LCC Key Generation for IoT Sensor Nodes

  • Conference paper
  • First Online:
Microelectronics, Electromagnetics and Telecommunications

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 655))

Abstract

IoT which enables data transmission through different kind’s interrelated networks, mostly the data is exchanged between wireless networks, and chances of hacking. Security is the most important aspect, and the data should be confidential to avoiding hacking. The cryptography solutions are utilized as an answer for improving security and the customary calculations because their limitation setting is not perfect for IoT gadgets. It is therefore possible to use the lightweight cryptographic algorithm as a solution to IoT security problems. However, there are a number of algorithms to choose from the distinctive execution criteria and conditions; the PRESENT cipher template in this paper is the encryption method using the 64-bit key for 64-bit data for hardware-level data protection input. To improve the security, Lorenz Chaotic Circuit with Dual-port Read Only Memory-based Present Algorithm (LCC-DROM-PA) architecture is proposed in this work, and for generating the key value, LCC is an essential design, and DROM is used for S-box design and P-layer design. After designing this architecture, FPGA performances are evaluated by the count of LUTs, flip-flops, slices, and frequency.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 169.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 219.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 219.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Okabe T (2016) Efficient FPGA implementations of print cipher. JETIR 3(4). ISSN-2349-5162

    Google Scholar 

  2. Akash D, Shanthi P (2016) Lightweight security algorithm for wireless node connected with IoT. Indian J Sci Technol 9(30). https://doi.org/10.17485/ijst/2016/v9i30/99035

  3. Karri R, Kuznetsov G, Goessel M (2003) Parity-based concurrent error detection of substitution-permutation network block ciphers. In: International workshop on cryptographic hardware and embedded systems. Springer, Berlin, Heidelberg

    Google Scholar 

  4. McKay KA, Bassham L, Turan MS, Mouha N (2017) Report on lightweight cryptography. US Department of Commerce, National Institute of Standards and Technology

    Google Scholar 

  5. Yalla P, Kaps J-P (2009) Lightweight cryptography for FPGAs. In: An international conference on reconfigurable computing and FPGAs—ReConFig’09, Dec 2009. IEEE, pp 225–230. https://doi.org/10.1109/ReConFig.2009.54

  6. Banik S, Bogdanov A, Isobe T, Shibutani K, Hiwatari H, Akishita T, Regazzoni F (2014) Midori: a block cipher for low energy. In: International conference on the theory and application of cryptology and information security. Springer, Berlin, Heidelberg

    Google Scholar 

  7. Venugopal M, Doraipandian M (2017) Lightweight cryptographic solution for IoT—an assessment. Int J Pure Appl Math 117(16):511–516

    Google Scholar 

  8. Książak P, Farrelly W, Curran K (2014) A lightweight authentication protocol for secure communications between resource-limited devices and wireless sensor networks. Int J Inf Secur Privacy 8(4):62–102

    Google Scholar 

  9. Jyothirmayi G, Madhu GC (2018) Present cipher architecture implementation on Xilinx 14.3. IJEECS 7(4). ISSN: 2348-117x

    Google Scholar 

  10. Reddy PP, Thrimurthulu V, Kumar KJ (2014) Implementation of multi mode AES algorithm using Verilog. Int J Eng Res 3(12):780–785. ISSN: 2319-6890

    Google Scholar 

  11. Panasenko S, Smagin S (2011) Lightweight cryptography: underlying principles and approaches. Int J Comput Theory Eng 3(4)

    Google Scholar 

  12. Chaitra B, Kiran Kumar VG, Shatharama Rai C (2017) A survey on various lightweight cryptographic algorithms on FPGA. IOSR J Electron Commun Eng 12(1):54–59, Ver. II. E-ISSN: 2278-2834, P-ISSN: 2278-8735

    Google Scholar 

  13. Bogdanov A, Leander G, Knudsen LR, Paar C, Poschmann A, Robshaw MJ, Seurin Y, Vikkelsoe C (2007) Present—an ultra-lightweight block cipher. In: Proceedings of CHES 2007. Lecture notes in computer science, vol 4727. Springer-Verlag, pp 450–466 [Online]. Available: https://doi.org/10.1007/978-3-540-74735-2_31

  14. Anurupam K (2018) Dynamic S-box implementation in present cipher. Int J Comput Sci Eng 6(9). E-ISSN: 2347-2693

    Google Scholar 

  15. Suresh H, Vignesh Chandrasekhar R (2018) Lightweight hardware architectures for present cipher in FPGA. IJEDR 6(1). ISSN: 2321-9939

    Google Scholar 

  16. Azari HD, Joshi PV (2018) An efficient implementation of present cipher model with 80 bit and 128 bit key over FPGA based hardware architecture. Int J Pure Appl Math 119(4):1825–1832

    Google Scholar 

  17. Gomez E, Hernández C, Martinez F (2017) Performance evaluation of the present cryptographic algorithm over FPGA. Contemp Eng Sci 10(12), 555–567. https://doi.org/10.12988/ces.2017.7653

  18. Guan Z-H, Huang F, Guan W (2005) Chaos-based image encryption algorithm. Elsevier B.V. https://doi.org/10.1016/j.physleta.2005.08.006

  19. Lara-Nino CA, Morales-Sandoval M, Diaz-Perez A (2016) Novel FPGA-based low-cost hardware architecture for the present block cipher. In: 2016 Euromicro conference on digital system design. IEEE. ISBN: 978-1-5090-2817-7/16. https://doi.org/10.1109/dsd.2016.46

  20. Hanley N, O’Neill M (2012) Hardware comparison of the ISO/IEC 29192-2 block ciphers. In: Proceedings of IEEE computer society annual symposium on VLSI (ISVLSI), pp 57–62

    Google Scholar 

  21. Lara-Nino CA, Diaz-Perez A, Morales-Sandoval M (2017) Lightweight hardware architectures for the present cipher in FPGA. IEEE. ISSN: 1549-8328

    Google Scholar 

  22. Ali-Pacha A, Hadj-Said N, M’Hamed A, Belgoraf A (2007) Lorenz’s attractor applied to the stream cipher (Ali-Pacha generator). Chaos Soliton Fract 33(5):1762–1766

    Google Scholar 

  23. Merah L, Ali-Pacha A, Said NH, Mamat M (2013) Design and FPGA implementation of Lorenz chaotic system for information security issues. Appl Math Sci 7(5):237–246

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, GITAM (Deemed to be University), Visakhapatnam, India

    Srikanth Parikibandla & Alluri Sreenivas

Authors
  1. Srikanth Parikibandla
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Alluri Sreenivas
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Srikanth Parikibandla .

Editor information

Editors and Affiliations

  1. Department of Electronics and Communication Engineering, Raghu Institute of Technology, Visakhapatnam, Andhra Pradesh, India

    P. Satish Rama Chowdary

  2. Department of Electronics and Communication Engineering, Raghu Institute of Technology, Visakhapatnam, Andhra Pradesh, India

    V.V.S.S.S. Chakravarthy

  3. Department of Electronics and Telecommunication Engineering, Universitat Ramon Llull, Barcelona, Spain

    Jaume Anguera

  4. School of Computer Engineering, KIIT University, Bhubaneswar, Odisha, India

    Suresh Chandra Satapathy

  5. Department of Electronics and Communication Engineering, Shri Ramswaroop Memorial Group of Professional Colleges (SRMGPC), Lucknow, Uttar Pradesh, India

    Vikrant Bhateja

Rights and permissions

Reprints and permissions

Copyright information

© 2021 Springer Nature Singapore Pte Ltd.

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Parikibandla, S., Sreenivas, A. (2021). FPGA Performance Evaluation of Present Cipher Using LCC Key Generation for IoT Sensor Nodes. In: Chowdary, P., Chakravarthy, V., Anguera, J., Satapathy, S., Bhateja, V. (eds) Microelectronics, Electromagnetics and Telecommunications. Lecture Notes in Electrical Engineering, vol 655. Springer, Singapore. https://doi.org/10.1007/978-981-15-3828-5_39

Download citation

  • DOI: https://doi.org/10.1007/978-981-15-3828-5_39

  • Published:

  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-15-3827-8

  • Online ISBN: 978-981-15-3828-5

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation