Abstract
Advancement in CMOS technology has made the Static Random Access Memory (SRAM) design to be very demanding. The designers face several challenges in improving the performance by improving read stability, write ability and leakage power. The design in the proposed design uses power gating strategy to lower leakage power. It is known that for 2 bit-line scheme of SRAM, some amount of power is wasted in the form of charging or discharging the bit-lines. The design in the proposed cell dissipates 67.7% less leakage power, 58.18% less writing power and 70.78% less reading power when compared to the double bit-line SRAM at 1 V of supply voltage. In addition to it, the design has good read stability, write ability and better read/write performance.
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References
Yang S, Wang W, Vijaykrishnan N, Xie Y (2005) Low leakage robust SRAM cell design for sub-100 nm technologies. In: Proceedings of ASP-DAC, pp 539–544
Samandari-Rad J, Guthaus M, Hughey R (2014) Confronting the variability issues affecting the performance of next-generation SRAM design to optimize and predict the speed and yield. IEEE Acess 2:577–601
Tu MH, Lin JY, Tsai MC, Jou SJ, Chuang CT (2010) Single-ended subthreshold SRAM with asymmetrical write/read-assist. IEEE Trans Circuits Syst I Reg Papers 57(12):303–3047
Chiu YW et al. (2014) 40 nm bit-interleaving 12T subthreshold SRAM with data-aware write-assist. IEEE Trans Circuits Syst I Reg Papers 61(9):2578–2585
Islam A, Hasan M (2012) Leakage characterization of 10T SRAM cell. IEEE Trans Electron Devices 59(3):631–638
Aly RE, Bayoumi MA (2007) Low-power cache design using 7T SRAM cell. IEEE Trans Circuits Syst II Exp Breifs 54(4):318–322
Chang L et al (2005) Stable SRAM cell design for the 32 nm node and beyond. In: Proceedings of the symposium on VLSI technology, pp 128–129
Liu Z Kursun V (2008) Characterization of a novel nine-transistor SRAM cell. IEEE Trans Very Large Scale Integr (VLSI) Syst 16(4):488–492
Chang IJ, Kim JJ, Park SP, Roy K (2008) A 32 kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS. In: Proceedings of IEEE International Solid State and Circuits Conference, Feb, pp 388–622
Seevinck Evert, List Frans J, Lohstroh Jan (1987) Static noise margin analysis of MOS SRAM cells. IEEE J Solid-State Circuits 22(5):748–754
Grossar Evelyn, Stucchi Michele, Maex Karen, Dehane Wim (2006) Read stability and write ability analysis of SRAM cells for nanometer technologies. IEEE J Solid State Circuits 41(11):2577–2588
Lindert N, Chang L, Choi YK, Anderson EH, Lee WC, King TJ, Bokor J, HuC (2001) Sub-60 nm quasi-planar FinFETs fabricated using a simplified process. IEEE Electron Device Lett 22(10):487–489
Wen L, Li Z, Li Y (2013) Single-ended, robust 8T SRAM cell for low-voltage operation. Microelectron J 44(8):718–728
Kulkarni JP, Kim K, Roy K (2007) A 160 m V Robust Schmitt trigger based sub threshold SRAM. IEEE J Solid-State Circuits 42(10)
Kulkarni JP, Roy K (2012) Ultralow-voltage process-variation-tolerant Schmitt-trigger-based SRAM design. IEEE Trans Very Large Scale Integr (VLSI) Syst 20(2):319–332
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Vijapur, P.R., Uma, B.V. (2020). Single-Ended Low Power Robust 9T Static Random Access Memory Using FinFETs. In: Kadambi, G., Kumar, P., Palade, V. (eds) Emerging Trends in Photonics, Signal Processing and Communication Engineering. Lecture Notes in Electrical Engineering, vol 649. Springer, Singapore. https://doi.org/10.1007/978-981-15-3477-5_12
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DOI: https://doi.org/10.1007/978-981-15-3477-5_12
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