Abstract
Reduced frequency and area-efficient streaming applications using clock gating and BUFGCE technique are presented in the paper. The clock-gating methodology consists of a different microcontroller, logic gates, flip-flop, and buffer. We used four controllers and a logic gate. The experimental results show that area is reduced to 26%, frequency 630.14 MHz, and thereby reducing the dynamic power without any fall in output data.
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Lavanya, N., Harikrishna, B., Kalpana, K. (2020). Reduced Frequency and Area Efficient for Streaming Applications Using Clock Gating and BUFGCE Technology. In: Solanki, V., Hoang, M., Lu, Z., Pattnaik, P. (eds) Intelligent Computing in Engineering. Advances in Intelligent Systems and Computing, vol 1125. Springer, Singapore. https://doi.org/10.1007/978-981-15-2780-7_49
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DOI: https://doi.org/10.1007/978-981-15-2780-7_49
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