Abstract
Efficiently executing the massively parallel applications has become an important goal of developing a modern high-performance multicore computer. In these parallel programs, the collective communication among these cores consume a large portion of inter-core communication. In order to prevent the collective communication from the performance bottleneck of the on-chip network, this paper proposed a new on-chip network, call Hierarchy Self Similar Cubic (HSSC), to reduce the latency of the collective communication on the multicore system. The corresponding transmission mechanisms and packet scheduling mechanism are proposed to analyze and grouping the packets, and determine a suitable transmission mechanism for each packet group on-the-fly. The experiments compare the performance of several on-chip networks. The advantages of proposed transmission mechanisms and packet scheduling mechanism are also discussed.
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Acknowledgments
This work is supported in part by the Ministry of Science and Technology of Republic of China, Taiwan under Grant MOST 105-2221-E-033-047.
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Chu, SL., Ho, WC., Jiang, YJ. (2020). Improving the Performance of Collective Communication for the On-Chip Network. In: Shen, H., Sang, Y. (eds) Parallel Architectures, Algorithms and Programming. PAAP 2019. Communications in Computer and Information Science, vol 1163. Springer, Singapore. https://doi.org/10.1007/978-981-15-2767-8_5
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DOI: https://doi.org/10.1007/978-981-15-2767-8_5
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