Abstract
RISC-V (Reduced Instruction Set Computer-Five) is an emerging universal open ISA, targeting to become as popular for processors as Linux for operating systems. Currently, many research institutions and companies publish various RISC-V processor cores. One of the most important feature of processors is the ability to response to interrupt events. This paper studies the interrupt mechanism of Hummingbird e203, which is an open-source RISC-V processor. By analyzing the existing interrupt mechanism, we propose a new mechanism of interrupt vectorization, which can achieve faster interrupt response. We also carry out simulation and logical synthesising for these two different response mechanism. Theoretical analyzing and evaluation results show that our design is feasible and efficient, improving the response speed to 1.6x–3.5x.
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Xu, K., Li, Y., Yuan, B., Su, D. (2019). Evaluation and Optimization of Interrupt Response Mechanism in RISC-V Architecture. In: Xu, W., Xiao, L., Li, J., Zhu, Z. (eds) Computer Engineering and Technology. NCCET 2019. Communications in Computer and Information Science, vol 1146. Springer, Singapore. https://doi.org/10.1007/978-981-15-1850-8_17
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DOI: https://doi.org/10.1007/978-981-15-1850-8_17
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