Hardware Security in India: The Journey so Far

Part of the IITK Directions book series (IITKD, volume 4)


Hardware Security is relatively a young discourse when compared to its more classical counterparts, like cryptography or network security. Yet, the growth of this subject in spite of his short history is phenomenal and the impetus of it in the modern-day world is striking. Like other parts of the world, India also joined this important area of research from the last decade to cover important areas in this discourse. This article is a description of some of the core subareas from our country, which includes cryptographic hardware design, side-channel analysis, fault analysis, micro-architectural attacks, Trojan detections, physically unclonable functions, and applications in IoT security. The chapter concludes with some ongoing efforts in the country to extend the core competence developed to develop secured end–end cyber-physical systems, which is of immense importance not only in our country, but also in the rest of the world.


VLSI of cryptographic algorithms Side-channel analysis Countermeasures Fault tolerance Micro-architectural attacks PUFs IoT security 



The author would like to thank, in particular, his former and present Masters and Ph.D students at the SEAL Lab, IIT Kharagpur for the various collaborations and findings. In particular, he would like to thank Arnab Bag, Durba Chatterjee, Debapriya Basu Roy, Manaar Alam, Sarani Bhattacharya, Sayandeep Saha, Sikhar Patranabis, Urbi Chatterjee for several discussions during the writing of this article.


  1. 1.
    Kocher P, Jaffe J, Jon B Differential power analysis. Advances in cryptology CRYPTO99. Springer, pp 388–397 (1999)Google Scholar
  2. 2.
    Boneh D, Millo R, Lipton R (1997) On the importance of checking cryptographic protocols for faults. Advances in cryptology EUROCRYPT97. Springer, pp 37–51Google Scholar
  3. 3.
    Biham E, Shamir A (1997) Differential fault analysis of secret key cryptosystems. In: B.S.K. Jr. (ed) Advances in cryptology–CRYPTO 1997. Lecture Notes in Computer Science, vol 1294. Springer, pp 513–525Google Scholar
  4. 4.
    Hankerson D, Menezes AJ, Vanstone S (2006) Guide to elliptic curve cryptography. Springer Science & Business MediaGoogle Scholar
  5. 5.
    Christopher, ST (2010) Tarnovsky hacks infineon’s ’unhackable’ chip, we prepare for false-advertising litigation.
  6. 6.
    Sparks ER (2007) A security assessment of trusted platform modules. Technical report, Department of Computer Science Dartmouth College.
  7. 7.
    Pappu RS, Ravikanth PS, Recht B, Taylor J, Gershenfeld N (2002) Physical one-way functions. Science 297:2026–2030Google Scholar
  8. 8.
    Tunstall M, Mukhopadhyay D, Ali S (2011) Differential fault analysis of the advanced encryption standard using a single fault. In: Information security theory and and privacy of mobile devices in wireless communication, Springer pp 224–233Google Scholar
  9. 9.
    Tupsamudre H, Bisht S, Mukhopadhyay D (2014) Destroying fault invariant with randomization. In: Cryptographic hardware and embedded systems–CHES 2014, Springer, pp 93–111Google Scholar
  10. 10.
    Saha S, Mukhopadhyay D, Dasgupta P (2018) ExpFault: an automated framework for exploitable fault characterization in block ciphers. IACR Trans Cryptogr Hardw Embed Syst 2018(2):242–276Google Scholar
  11. 11.
    Saha S, Jap D, Patranabis S, Mukhopadhyay D, Bhasin S, Dasgupta P (2018) Automatic characterization of exploitable faults: A machine learning approach. IEEE Trans Inf Forensics Secur 1 (to appear).
  12. 12.
    Güneysu T, Paar C (2008) Ultra high performance ecc over nist primes on commercial fpgas. In: International workshop on cryptographic hardware and embedded systems, Springer, pp 62–78Google Scholar
  13. 13.
    Rebeiro C, Roy SS, Mukhopadhyay D (2012) Pushing the limits of high-speed gf (2 m) elliptic curve scalar multiplication on fpgas. In: International workshop on cryptographic hardware and embedded systems, Springer, pp 494–511Google Scholar
  14. 14.
    Roy SS, Rebeiro C, Mukhopadhyay D (2013) Theoretical modeling of elliptic curve scalar multiplier on lut-based fpgas for area and speed. IEEE Trans Very Large Scale Integr (VLSI) Syst 21(5):901–909Google Scholar
  15. 15.
    Roy DB, Mukhopadhyay D, Izumi M, Takahashi J (2014) Tile before multiplication: an efficient strategy to optimize DSP multiplier for accelerating prime field ecc for nist curves. In: Proceedings of the 51st annual design automation conference, ACM, pp 1–6Google Scholar
  16. 16.
    Roy DB, Das P, Mukhopadhyay D (2015) Ecc on your fingertips: a single instruction approach for lightweight ecc design in gf (p). In: International conference on selected areas in cryptography, Springer, pp 161–177Google Scholar
  17. 17.
    Becker GT (2015) The gap between promise and reality: on the insecurity of xor arbiter pufs. In: International workshop on cryptographic hardware and embedded systems, Springer pp 535–555Google Scholar
  18. 18.
    Sahoo DP, Mukhopadhyay D, Chakraborty RS, Nguyen PH (2018) A multiplexer-based arbiter puf composition with enhanced reliability and security. IEEE Trans Comput 67(3):403–417MathSciNetCrossRefGoogle Scholar
  19. 19.
    Chatterjee U, Govindan V, Sadhukhan R, Mukhopadhyay D, Chakraborty RS, Mahata D, Prabhu MM (2018) Building puf based authentication and key exchange protocol for iot without explicit crps in verifier database. IEEE Trans Dependable Secur Comput 1 10.1109/TDSC.2018.2832201Google Scholar
  20. 20.
    Rebeiro C, Mukhopadhyay D (2008) High speed compact elliptic curve cryptoprocessor for fpga platforms. In: International conference on cryptology in India, Springer, pp 376–388Google Scholar
  21. 21.
    Rebeiro C, Mukhopadhyay D, Bhattacharya S (2014) Timing channels in cryptography: a micro-architectural perspective. SpringerGoogle Scholar
  22. 22.
    Bernstein DJ (2005) Cache-timing attacks on aes. Technical reportGoogle Scholar
  23. 23.
    Bhattacharya S, Mukhopadhyay D (2015) Who watches the watchmen?: utilizing performance monitors for compromising keys of RSA on intel platforms. In: CHES. Lecture Notes in Computer Science, vol 9293. Springer, pp 248–266Google Scholar
  24. 24.
    Bhattacharya S, Mukhopadhyay D (2018) Utilizing performance counters for compromising public key ciphers. ACM Trans Priv Secur 21(1) 5:1–5:31Google Scholar
  25. 25.
    Bhattacharya S, Mukhopadhyay D (2016) Curious case of rowhammer: flipping secret exponent bits using timing analysis. In: CHES. Lecture Notes in Computer Science, vol 9813. Springer, pp 602–624Google Scholar
  26. 26.
    Liu F, Lee RB (2014) Random fill cache architecture. In: Proceedings of the 47th annual IEEE/ACM international symposium on microarchitecture, IEEE Computer Society, pp 203–215Google Scholar
  27. 27.
    Martin R, Demme J, Sethumadhavan S (2012) Timewarp: rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacks. ACM SIGARCH Comput Arch News 40(3):118–129CrossRefGoogle Scholar
  28. 28.
    Alam M, Bhattacharya S, Mukhopadhyay D, Bhattacharya S (2017) Performance counters to rescue: a machine learning based safeguard against micro-architectural side-channel-attacksGoogle Scholar
  29. 29.
    Rebeiro C, Mukhopadhyay D, Takahashi J, Fukunaga T (2009) Cache timing attacks on clefia. In: International conference on cryptology in India, Springer, pp 104–118Google Scholar
  30. 30.
    Lai S, Patranabis S, Sakzad A, Liu J, Mukhopadhyay D, Steinfeld R, Sun S, Liu D (2018) Result pattern hiding searchable encryption for conjunctive queries. In: Proceedings of the 2018 ACM conference on computer and communications security (To Appear)Google Scholar
  31. 31.
    Bag A, Patranabis S, Tribhuvan L, Mukhopadhyay D (2018) POSTER: hardware acceleration for searchable encryption. In: Proceedings of the 2018 ACM conference on computer and communications security (To Appear)Google Scholar

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© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.Indian Institute of Technology KharagpurKharagpurIndia

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