Abstract
The demand for low power devices is exponentially increasing with the increase in the use of portable equipment such as laptops and mobile phones. Adiabatic logic is an emerging technique which proves to be efficient in reducing the power dissipation of the system. Positive Feedback Adiabatic Logic (PFAL) is an efficient adiabatic logic. Multipliers are the fundamental arithmetic operators in the digital circuits. Addition is the integral part of multiplication, to add the partial products. A 16-bit Wallace Tree Multiplier (WTM) is implemented using carry-save addition. The Conventional WTM (CWTM) is modified to minimize complexity, termed as Reduced Complexity WTM (RCWTM) which has minimum number of Half Adders compared to the CWTM, which results in the reduction of the WTM area. The RCWTM is designed using both static CMOS logic and PFAL. The design is analyzed in Cadence Virtuoso 180 nm technology and simulated in Cadence Spectre. The PFAL based RCWTM dissipates 81.8% less power compared to static CMOS design.
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References
Biradar, V.B., Vishwas, P.G., Chetan, C.S., Premananda, B.S.: Design and performance analysis of modified unsigned braun and signed Baugh-Wooley multiplier. In: Proceedings of the International Conference on Electrical, Electronics, Communication, Computer and Optimization Techniques, pp. 1–6 (2017)
Bennet, B., Maflin, S.: Modified energy efficient carry save adder. In: Proceedings of the International Conference on Circuits, Power and Computing Technologies, pp. 1–4 (2015)
Kaur, J., Sood, L.: Comparison between various types of adder topologies. Int. J. Comput. Sci. Technol. 6, 62–66 (2015)
Alam, S., Ghimiray, S.R., Kumar, M.: Performance analysis of a 4-bit comparator circuit using different adiabatic logics. In: Innovations in Power and Advanced Computing Technologies, pp. 1–5 (2017)
Premananda, B.S., Chandana, M.K., Shree Lakshmi, K.P., Keerthi, A.M.: Design of low power 8-bit carry select adder using adiabatic logic. In: Proceedings of the International Conference on Communication and Signal Processing, pp. 1764–1768 (2017)
Chinnapparaj, S., Somasundareswari, D.: Incorporation of reduced FA and HA into WTM and improved CSA for digital FIR filter. Int. J. Circuits Syst. 7, 2467–2475 (2016)
Mandloi, A., Agrawal, S., Sharma, S., Shrivastava, S.: High-speed, area efficient VLSI architecture of Wallace-Tree Multiplier for DSP-applications. In: Proceedings of the International Conference on Information, Communication, Instrumentation and Control, pp. 1–5 (2017)
Jaiswal, K.B., Nithish Kumar, V., Seshadri, P., Laksminaryan, G.: Low power Wallace Tree Multiplier using modified full adder. In: Proceedings of the 3rd International Conference on Signal Processing, Communication and Networking, pp. 1–4 (2015)
Vijay, A.J., Krishnamurthy, M.: Design of area and power aware reduced Wallace Tree Multiplier. Int. J. Adv. Res. Electron. Commun. Eng. 6, 1241–1244 (2017)
Waters, R.S., Swatzlander, E.E.: A reduced complexity Wallace multiplier reduction. IEEE Trans. Comput. 59, 1134–1137 (2010)
Bhati, P., Rizvi, N.: Adiabatic logic: an alternative approach to low power application circuits. In: Proceedings of the IEEE International Conference on Electrical, Electronics, and Optimization Techniques, pp. 4255–4260 (2016)
Kumar, S.D., Thapliyal, H., Mohammad, A.: FinSAL: A Novel FinFET based secure adiabatic logic for energy-efficient and DPA resistant IoT devices. In: Proceedings of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, pp. 110–122 (2018)
Kumawat, P.K., Sujediya, G.: Design and comparison of 8 × 8 Wallace Tree Multiplier using CMOS and GDI technology. IOSR J. VLSI Sig. Process. 7, 2319–4197 (2017)
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Ganavi, M.G., Premananda, B.S. (2020). Design of Low Power Reduced Complexity Wallace Tree Multiplier Using Positive Feedback Adiabatic Logic. In: Pati, B., Panigrahi, C., Buyya, R., Li, KC. (eds) Advanced Computing and Intelligent Engineering. Advances in Intelligent Systems and Computing, vol 1089. Springer, Singapore. https://doi.org/10.1007/978-981-15-1483-8_13
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DOI: https://doi.org/10.1007/978-981-15-1483-8_13
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