Abstract
In this paper, the performance of the different structures of XOR/XNOR circuit has been evaluated. The non-full swing output voltage level and power delay product (PDP) of the earlier structures has been improved in the proposed XOR/XNOR circuit. The performance of the proposed circuit has been investigated in terms of full swing output voltage, total power dissipation and computational delay using Pyxis Schematics Tool of Mentor Graphics. The Simulation is based on TSMC018 CMOS technology model file.
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Gupta, M., Pandey, B.P., Chauhan, R.K. (2020). CMOS-Based XOR Gate Design for Full Swing Output Voltage and Minimum Power Delay Product (PDP). In: Bhateja, V., Satapathy, S., Zhang, YD., Aradhya, V. (eds) Intelligent Computing and Communication. ICICC 2019. Advances in Intelligent Systems and Computing, vol 1034. Springer, Singapore. https://doi.org/10.1007/978-981-15-1084-7_11
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DOI: https://doi.org/10.1007/978-981-15-1084-7_11
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