Abstract
The demand of higher capacity, smaller size, and reliable memory is increasing with the continuous scaling of semiconductor technology with time. But reliability of memory is greatly influenced by soft errors caused due to radiation effects. These soft errors lead to corruption of data stored in one or multiple cells of memory. Error Correction Codes (ECCs) are frequently employed for mitigating the effects of soft errors in memories. Single Error Correction-Double Error Detection-Double Adjacent Errors Correction (SEC-DED-DAEC) code is one of the popularly known ECC schemes which is employed when Multiple Bit Upsets (MBUs) occur in memory. In this paper, a new SEC-DED-DAEC code has been proposed for memory applications. The proposed codecs have been designed and synthesized in FPGA platform for some common word lengths frequently used in memory applications. The performance of proposed codecs have been compared with other related works. The proposed codecs require lesser area compared to existing codecs.
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Maity, R.K., Samanta, J., Bhaumik, J. (2020). New Compact SEC-DED-DAEC Code for Memory Applications. In: Kundu, S., Acharya, U.S., De, C.K., Mukherjee, S. (eds) Proceedings of the 2nd International Conference on Communication, Devices and Computing. ICCDC 2019. Lecture Notes in Electrical Engineering, vol 602. Springer, Singapore. https://doi.org/10.1007/978-981-15-0829-5_32
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DOI: https://doi.org/10.1007/978-981-15-0829-5_32
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