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Strained Silicon Technology

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Book cover Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond

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Abstract

With transistor dimension shrinking into nanoscale regime as described in the previous chapter, conventional gate oxide thickness has been scaled near the thickness limit of 1 nm. This scaling trend brings issues about power consumption, transistor density and off-leakage current, together with carrier mobility degradation. Furthermore, the continuous scaling-down of device dimensions and further performance enhancement are facing more and more severe challenges.

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Authors and Affiliations

  1. Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, 100029, China

    Guilei Wang

  2. University of Chinese Academy of Sciences, Beijing, China

    Guilei Wang

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  1. Guilei Wang
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Correspondence to Guilei Wang .

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Wang, G. (2019). Strained Silicon Technology. In: Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond. Springer Theses. Springer, Singapore. https://doi.org/10.1007/978-981-15-0046-6_2

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  • DOI: https://doi.org/10.1007/978-981-15-0046-6_2

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-15-0045-9

  • Online ISBN: 978-981-15-0046-6

  • eBook Packages: Physics and AstronomyPhysics and Astronomy (R0)

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