Implementation of Array Logic Functions Using Mixed Logic Design Methodology for Low-Power High-Speed Applications

Abstract

The novel design techniques in nanoscale circuits are essential for advanced and high-performance VLSI domain circuits. This paper brings a novel design methodology, i.e., mixed logic style includes High skew (Hi-Skew), Low skew (Lo-Skew), Transmission Gate Logic (TGL), Pass Transistor Logic (PTL), to realize line decoders. Several designs are proposed on 2 × 4 line decoders by combining four logic styles. The advantage of reduced transistors counts: reuse of already available signals, low contribution to the static power consumption of pass transistors, fully restored logic gate of the transmission gate, making one input transition more valuable compared to other of skew gates; it is possible to design the high-performance VLSI circuits. Moreover, the quality metric of the circuit is improved. Various designs are proposed. All these proposed designs are simulated with BSIM 32 nm predictive technology model. The comparative analysis of circuits is done at the various frequency of operations (500 MHz, 1, 2 Ghz) and at different power supplies (0.8, 1.0, 1.2 V). The simulation results showed that a significant reduction in power consumption, propagation delay, and other quality matrices (PDP, etc.,) compared to existing static and other mixed logic design circuits. Therefore, mixed logics are well suited for the design and implantation of array logic.