Skip to main content

Arithmetic Circuits Using Reversible Logic: A Survey Report

  • Chapter
  • First Online:
Advanced Computing and Systems for Security

Part of the book series: Advances in Intelligent Systems and Computing ((AISC,volume 995))

Abstract

In this paper, a survey has been made on the design of arithmeticĀ circuits like adder, subtractor, multiplier, and squarer. There are many design schemes for those arithmetic circuits some of which have beenĀ studied and described in this paper.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Landauer, R.: Irreversibility and heat generation in the computing process. IBM J. Res. Dev. 5, 183 (1961)

    ArticleĀ  MathSciNetĀ  Google ScholarĀ 

  2. Castello, D.J., Forney, G.D.: Cannel coding: the road to cannel capacity. Proc. IEEE. 95(6), 1150ā€“1177 (2007)

    ArticleĀ  Google ScholarĀ 

  3. Bennett, C.H.: Logical reversibility of computation. IBM J. Res. Dev. 17(6), 525ā€“532 (1973)

    ArticleĀ  MathSciNetĀ  Google ScholarĀ 

  4. Berut, A., Arakelyan, A., Petrosyan, A., Ciliberto, S., Dillenschneider, R., Lutz, E.: Experimental verification of landauer/ā€™s principle linking information and thermodynamics. Nature 483(7388), 187ā€“189 (2012)

    ArticleĀ  Google ScholarĀ 

  5. Hong, S., Kim, S., Papaefthymiou, M.C., Stark, W.E.: Low power parallel multiplier design for dsp applications through co-efficient optimization. In: IEEE International Conference on ASIC/SOC, pp. 286ā€“290 (1999)

    Google ScholarĀ 

  6. Bulic, P., Babic, Z., Avramovic, A.: A simple pipelined logarithmic multiplier. In: IEEE International Conference on Computer Design, pp. 235ā€“240, October 2010

    Google ScholarĀ 

  7. Mrazek, V., Sarwar, S.S., Sekanina, L., Vasicek, Z., Roy, K.: Design of power-efficient approximate multipliers for approximate artificial neural networks. In: IEEE/ACM International Conference on Computer-Aided Design, pp. 1ā€“7 (2016)

    Google ScholarĀ 

  8. Venkatachalam, S., Ko, S.B.: Design of power and area efficient approximate multipliers. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25(5), pp. 1782ā€“1786 (2017)

    ArticleĀ  Google ScholarĀ 

  9. Yoo, J.T., Smith, K.F., Gopalakrishnan, G.: A fast parallel squarer based on divide-and-conquer. IEEE J. Solid-State Circuits 32, 909912 (June 1997)

    ArticleĀ  Google ScholarĀ 

  10. Deshpande, A., Draper, J.: Comparing squaring and cubing units with multipliers. In: IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 466ā€“469 (2012)

    Google ScholarĀ 

  11. Datla, S.R., Thornton, M.A., Matula, D.W.: A low power high performance radix-4 approximate squaring circuit. In: 20th IEEE International Conference on Application Specific Systems, Architectures and Processors (ASAP), Vol.Ā 7, pp. 91ā€“97 (July 2009)

    Google ScholarĀ 

  12. Jayashree, H.V., Thapliyal, H., Agrawal, V.K.: Design of dedicated reversible quantum circuitry for square computation. In: Proceedings of 27th International Conference on VLSI Design, pp. 551ā€“556 (January 2014)

    Google ScholarĀ 

  13. Kotiyal, S., Thapliyal, H., Ranganathan, N.: Circuit for reversible quantum multiplier based on binary tree optimizing ancilla and garbage bits. In: Proceedings of 27th International Conferenceon VLSI Design, pp. 545ā€“550 (January 2014)

    Google ScholarĀ 

  14. Thapliyal, H., Ranganathan, N.: Design of efficient reversible logic based binary and bcd adder circuits. ACM J. Emerging Technol. Comput. Syst. 9(3), 17:1ā€“17:31 (September 2013)

    ArticleĀ  Google ScholarĀ 

  15. Thapliyal, H., Ranganathan, N., Kotiyal, S.: Design of testable reversible sequential circuits. IEEE Trans. VLSI 21(7), 1201ā€“1209 (2013)

    ArticleĀ  Google ScholarĀ 

  16. Thakre, A.K., Chiwande, S.S., Chafale, S.D.: Design of low power multiplier using reversible logic gate. In: Proceedings of International Conference on Green Computing Communication and Electrical Engineering (6ā€“8 March 2014)

    Google ScholarĀ 

  17. Madhulika, C., Nayak, V.S.P., Prasanth, C., Praveen, T.H.S.: Design of systolic array multiplier circuit using reversible logic. In: 2017 2nd IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, pp. 1670ā€“1673 (2017)

    Google ScholarĀ 

  18. Wille, R., Drechsler, R.: Towards a Design Flow for Reversible Logic. Springer (2010)

    Google ScholarĀ 

  19. Peres, A.: Reversible logic and quantum computers. APS Phys. Rev. A 32, 3266ā€“3276 (1985)

    ArticleĀ  MathSciNetĀ  Google ScholarĀ 

  20. Cuccaro, S.A., Draper, T.G., Kutin, S.A.: A new quantum ripple-carry addition circuit. arXiv:quant-ph/0410184. (February 2008)

  21. Thapliyal, H., Arabnia, H., Srinivas, M.: Efficient reversible logic design of bcd subtractors. Springer Trans. Comput. Sci. J. 3(LNCS 5300), 99ā€“121 (2009)

    Google ScholarĀ 

  22. Thapliyal, H., Ranganathan, N.: A new design of the reversible subtractor circuit. In: Proceedings of the 11th IEEE International Conference on Nanotechnology (IEEE NANO), pp. 1430ā€“1435 (August 2011)

    Google ScholarĀ 

  23. Thapliyal, H., Srinivas, M.B.: Novel reversible multiplier architecture using reversible tsg gate. In: IEEE International Conference on Computer Systems and Applications, 8th March 2006

    Google ScholarĀ 

  24. Fredkin, E.F., Toffoli, T.: Conservative logic. Int. J. Theor. Phys. 21(3), 219ā€“253 (1982)

    ArticleĀ  MathSciNetĀ  Google ScholarĀ 

  25. Haghparast, M., Jassbi, S., Navi, K., Eshghi, M.: Optimized reversible multiplier circuits. J. Circuits Syst. Comput. 18, 311ā€“323 (2009)

    ArticleĀ  Google ScholarĀ 

  26. Karatsuba, A., Ofman, Y.: Multiplication of many-digital numbers by automatic computers. Doklady Akad. Nauk SSSR 145 (1963)

    Google ScholarĀ 

  27. Offermann, S., Wille, R., Dueck, G.W., Drechsler, R.: Synthesizing multiplier in reversible logic. In: 13th IEEE Symposium on DDECS, pp. 335ā€“340 (April 2010)

    Google ScholarĀ 

  28. Axelsen, H.B., Thomsen, M.K.: Garbage-free integer multiplication with constants of the form \(2^{k}\pm 2^{l}\pm 1\). In: 4th Workshop on Reversible Computation (July 2012)

    Google ScholarĀ 

  29. Saravanan, P., Chadrasekar, P., Chandran, L., Sriram, N., Kalpana, P.: Design and implementation of efficient vedic multiplier using reversible logic. In: International Symposium on VLSI Design and Test, pp. 364ā€“366 (2012)

    ChapterĀ  Google ScholarĀ 

  30. Banerjee, A., Das, D.K.: The design of reversible multiplier using ancient indian mathematics. In: International Symposium on Electronic Design, pp. 31ā€“35 (December 2013)

    Google ScholarĀ 

  31. Banerjee, A., Das, D.K.: The design of reversible signed multiplier using ancient indian mathematics. J. Low Power Electron. 11, 467ā€“478 (December 2015)

    ArticleĀ  Google ScholarĀ 

  32. Banerjee, A., Das, D.K.: Squaring in reversible logic using iterative structure. In: Proceedings of East West Design and Test Symposium (September 2014)

    Google ScholarĀ 

  33. Banerjee, A., Das, D.K.: Squaring in reversible logic using zero garbage and reduced ancillary inputs. In: International Conference on VLSI Design (2015)

    Google ScholarĀ 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Arindam Banerjee .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

Ā© 2020 Springer Nature Singapore Pte Ltd.

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Banerjee, A., Das, D.K. (2020). Arithmetic Circuits Using Reversible Logic: A Survey Report. In: Chaki, R., Cortesi, A., Saeed, K., Chaki, N. (eds) Advanced Computing and Systems for Security. Advances in Intelligent Systems and Computing, vol 995. Springer, Singapore. https://doi.org/10.1007/978-981-13-8962-7_8

Download citation

Publish with us

Policies and ethics