Bottleneck Crosstalk Minimization in Three-Layer Channel Routing

Abstract

Channel routing and crosstalk minimization are important concerns while we talk about high-performance circuits for two-, three-, and multilayer VLSI physical design automation. Interconnection among the net terminals satisfying constraints in an intelligent way is a necessity to realize a circuit within a minimum possible area, as this is a principal requirement to diminish cost as well as to augment yield. Introduction of a layer of interconnects may increase the cost of routing; however, as the area is minimized, cost is reduced as well. Eventually, the total wire length is also reduced. Therefore, there are several trade-offs. Besides, in high-performance routing, a designer is supposed to lessen the amount of electrical hazards, viz., crosstalk as much as possible. In this paper, we particularly work on minimizing bottleneck crosstalk in the three-layer HVH routing model. Here, along with area minimization, computed circuits’ performance has also been enhanced by computing precise bottleneck crosstalk HVH channel routing solutions. By the way, the specified crosstalk minimization problem is NP-hard. Thus, in this paper, heuristic algorithms have been devised for computing optimized bottleneck crosstalk channel routing solutions. Computed results of our proposed algorithms are greatly encouraging.