Abstract
The analog-to-digital converter is the key component for communication and signal processing. This paper describes the design and simulations of a 3-bit flash analog-to-digital converter (ADC) which includes voltage divider network, comparators, and a priority encoder. The proposed circuit is driven by 0.6 V supply voltage with an analog input of 600 mV amplitude and 1 MHz frequency. The proposed architecture is designed, simulated, and analyzed using Cadence Virtuoso IC 6.1.5 Simulator tool in 45-nm CMOS technology. The power consumption of proposed 3-bit flash ADC is 142 uW with 12.52 nS delay and output noise of 26.55 nV/sqrt(Hz). In this paper, a high-speed, low-power CMOS flash ADC, suitable for biomedical application, is proposed and analyzed.
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References
A. Mahesh Kumar, V. Tummala, Design of low power variable resolution flash ADC, in 22nd International Conference on VLSI Design (IEEE, 2009)
S.S. Guru, Dr. D.P. Acharya, Design and simulation of SIGMA DELTA ADC. M.Tech thesis, May (2013)
S. Mukherjee, D. Saha, P. Mostafa, D. Saha, S. Chatterjee, C.K. Sarkar, A low power, high speed, IF range flash type ADC designed with the concept of TMCC and Binary Counter, in IEEE (2012)
Pradeep, A, Mahaveera, K, Design and analysis of analog to digital converter for biomedical applications. Int. J. Innov. Res. Sci., Eng. Technol. 5(9) (2016). ISSN: 2319-8753
N. Prabhat, A. Yadav, A review of low power flash ADC using different comparator styles & design techniques. Int. J. Innov. Res. Comput. Commun. Eng. 4(Special Issue 4) (2016). ISSN (Online): 2320-9801
P.E. Allen, D.R. Holberg, CMOS Analog Circuit Design. 2nd edn. (Oxford University Press, 2004)
P.S. Nabeel, T.E. Ayoob Khan, Dr. T.A. Shahul Hameed Design of low power high speed flash ADC in 45 nm CMOS. Int. J. VLSI Syst. Des. Commun. Syst. (IJVDCS) 03(05), 0620–0625 (2015). ISSN 2322-0929
K. Chaudhary, R.B. Singh, A novel approach to 3-bit flash ADC. Int. J. Sci. Res. Dev. 2(03) (2014) Issn (Online): 2321-0613
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Firojuddin, S., Pal, S., Pain, P. (2020). Design and Comparative Analysis of Low-Power, High-Speed, 3-Bit Flash ADC for Biomedical Signal Processing Using 45-nm CMOS Technology. In: Maharatna, K., Kanjilal, M., Konar, S., Nandi, S., Das, K. (eds) Computational Advancement in Communication Circuits and Systems. Lecture Notes in Electrical Engineering, vol 575. Springer, Singapore. https://doi.org/10.1007/978-981-13-8687-9_30
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DOI: https://doi.org/10.1007/978-981-13-8687-9_30
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