Abstract
As we know for current industry, downscaling of MOSFET is a very essential factor, but due to downscaling, the performance of MOS degrades. For robust design, it is very much required to downscale the MOS length keeping the performance of MOSFET intact. The multigate MOS model has been introduced for keeping the MOS performance intact as well as reducing the channel length. In this paper, the comparison of 6-T single bit SRAM cell has been done using single-gate MOS and double-gate MOS in terms of power using CMOS technology and 90-nm channel length in SYMICA environment. SYMICA is an electronic design automation (EDA) tool for the analog and mixed-signal integrated circuit design. In this paper, we have simulated CMOS and DGMOS SRAM cell and compare the power dissipation of DGMOS SRAM cell and CMOS SRAM cell. It proves that the dynamic power consumption of DGMOS SRAM cell is much smaller than CMOS SRAM cell for a particular input voltage and channel length.
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Das (Roy), S., Panda, S., Chakraborty, G. (2020). Comparative Analysis of 6-T SRAM Cell in Terms of Power Using CMOS and DGMOS. In: Maharatna, K., Kanjilal, M., Konar, S., Nandi, S., Das, K. (eds) Computational Advancement in Communication Circuits and Systems. Lecture Notes in Electrical Engineering, vol 575. Springer, Singapore. https://doi.org/10.1007/978-981-13-8687-9_25
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DOI: https://doi.org/10.1007/978-981-13-8687-9_25
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