Abstract
The present paper is about design methodology of High speed Booth Encoded Multiplier. A Booth Multiplier consists of the Encoder, the partial product tree, carry propagate adder. The multiplicand and multiplier size (n) is 64-bit unsigned operands. Radix-16 Booth recoded multiplier is implemented using VHDL. To lessen the partial product addition, compressors are used. Using 3:2, 4:2, 5:2, 6:2, 7:2 compressors, and carry save and propagate adder, all partial products are added to get the final output product. The multiplier is implemented in VHDL using Xilinx.
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Madhuri, G.M.G., Kumari, C.A., Monica, C., Kumari, N.P. (2020). High Speed 64-Bit Booth Encoded Multiplier Using Compressor. In: Choudhury, S., Mishra, R., Mishra, R., Kumar, A. (eds) Intelligent Communication, Control and Devices. Advances in Intelligent Systems and Computing, vol 989. Springer, Singapore. https://doi.org/10.1007/978-981-13-8618-3_24
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DOI: https://doi.org/10.1007/978-981-13-8618-3_24
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