Abstract
A significant progress in design and fabrication processes for MEMS technology is observed in the last few decades, but the bottleneck of this technology is its packaging methodology which is around 70% of the total cost. Unlike the other microelectronics (VLSI/ULSI) devices, the main considerations for MEMS packages are to support free-hanging structures having small size and provide protection of mechanical membrane. Usually, the main functions of packages are providing mechanical support, protection from surrounding environment, and building electrical interconnection to other system components (Wartenberg in RF measurement of die and packages. Artech House Publication, 2002 [1]; Lim et al. in IEEE Microw Mag 3(1), 88–99, 2002 [2]; Tummala and Madisetti in IEEE Des Test Comput 16(2):48–56, 1999 [3]). Traditionally for many years, RF devices have been packaged in metal can, ceramic, and cerdip cavity packages. Among these, cavity packaging for the RF is most proffered in due to the consideration of providing headspace for raised surface features, such as air-bridges and protects elements such as RF-MEMS switch, phase shifter, filter, resonators, reconfigurable devices, etc.(Henderson and Katehi in IEEE Trans Microw Theory Tech 47(8): 1563–1569, 1999 [4]; Rebeiz et al. in Proceedings on 13th GaAs Symposium, Paris, 2005 [5]; Pelzer et al. in Proceedings on 6th international conference on electronic packaging technology, pp. 508–513, 2005 [6]; Iannacci et al. in Sens Actuators A 142: 434–441, 2008 [7]; Iannacci et al., in Proceedings of the IMAPS 2006 conference, San Diego, CA, 2006 [8]). This chapter primarily demonstrates standard cavity package modified for RF-MEMS application. It also highlights various approaches adopted to mitigate losses at Ka-band. At the higher end of microwave band, apart from the insertion and dielectric losses, radiation losses are also associated with the circuit. An FEM-based simulation study is carried out which provides the insight into the working of the RF package. This chapter provides insight of the each building block associated with the packaging and further detailing of the loss analysis. Further, Through Silicon Via (TSV) modeling is also included in this chapter. Nowadays most of the 3D packaging involves a compact and vertical integration technology, where TSV structures are integral part and modeling this aspect will provide an insight direction to a microwave engineer resulting in accurate prediction of the designed circuit.
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References
S.A. Wartenberg, RF Measurement of Die and Packages (Artech House Publication, 2002)
K. Lim, S. Pinel, M. Davis, A. Sutono, C.-H. Lee, D. Heo, A. Obatoynbo, J. Laskar, E.M. Tantzeris, R. Tummala, RF-System-On-Package (SOP) for wireless communications. IEEE Microw. Mag. 3(1), 88–99 (2002)
R. Tummala, V. Madisetti, System on chip or system on package? IEEE Des. Test Comput. 16(2), 48–56 (1999)
R.M. Henderson, L.P.B. Katehi, Silicon-based micromachined packages for high-frequency applications. IEEE Trans. Microw. Theory Tech. 47(8), 1563–1569 (1999)
G.M. Rebeiz et al., W-band low-loss wafer-scale package for RF MEMS, in Proceedings on 13th GaAs Symposium, Paris (2005)
R. Pelzer, H. Kirchberger, P. Ketnner, Wafer-to-wafer bonding techniques: from MEMS packaging to IC integration applications, in Proceedings on 6th International Conference on Electronic Packaging Technology, August 2005, pp. 508–513
J. Iannacci, M. Bartek, J. Tian, R. Gaddi, A. Gnudi, Electromagnetic optimization of an RF-MEMS wafer-level package. Sens. Actuators A 142, 434–441 (2008)
J. Iannacci, M. Bartek, J. Tian, S. Sosin, A. Akhnoukh, R. Gaddi, A. Gnudi, Hybrid wafer-level packaging for RF-MEMS applications, in Proceedings of the IMAPS 2006 Conference, San Diego, CA, October 2006
F. Gardiol, Microstrip Circuits (Wiley, 2013)
K. C. Gupta, R. Garg, R. Chadha, Computer Aided Design of Microwave Circuits (Artech House Publication, 1981)
T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits (Cambridge University Press, 1998)
M. Kamon, M.J. Tsuk, J.K. White, FASTHENRY: a multipole-accelerated 3-D inductance extraction program. IEEE Trans. Microw. Theory Tech. 42(9), 1750–1758 (1994)
Bond-wire modeling Standard, EIA/JEDEC Standard No. 59 (Electronic Industries Association, 1997)
HFSS ver.11.0 (Ansoft Corporation, USA), www.ansoft.com
R.R. Tummala, Fundamentals of Microsystems Packaging (McGraw-Hill Publication, New York, 2001)
M. Kobayashi, A dispersion formula satisfying recent requirements in microstrip CAD. IEEE Trans. MTT 36, 1246–1250 (1988)
E. Holtzman, Essentials of RF & Microwave Grounding (Artech House, 2006)
D.G. Swanson, Grounding microstrip lines with viaholes. IEEE Trans. Microw. Theory Tech. 40(8), 1719–1721 (1992)
D.G. Swanson, W.T.R. Hoefer, Microwave Circuit Modelling Using Electro-Magnetic Field Simulations (Artech House, 2003)
M.E. Goldfarb, R.A. Pucel, Modeling via hole grounds in microstrip. IEEE Microw. Guid. Wave Lett. 1(6), 135–137 (1991)
P. Kok, D. De Zutter, Capacitance of a circular symmetric model of a via hole including finite ground plane thickness. IEEE Trans. Microw. Theory Tech. 39, 1229–1234 (1991)
K.M. Strohm, P. Nuechler, C.N. Rheinfelder, R. Guehl, Via hole technology for microstrip TL & passive elements on high resistivity silicon. IEEE MTT-S Dig. 581–584 (1999)
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Karmakar, A., Singh, K. (2019). Packaging Concept in Radio Frequency. In: Si-RF Technology. Springer, Singapore. https://doi.org/10.1007/978-981-13-8051-8_6
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DOI: https://doi.org/10.1007/978-981-13-8051-8_6
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