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Design and FPGA Implementation of an High Efficient XGBoost Based Sleep Staging Algorithm Using Single Channel EEG

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Cognitive Systems and Signal Processing (ICCSIP 2018)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 1005))

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Abstract

This paper proposed a high efficient 5-class sleep staging XGBoost based algorithm using a single channel electroencephalogram (EEG). The sum of spectrum absolute value, instead of Fast Fourier Transform (FFT) based spectral energy, was proposed for feature extraction, which greatly reduced the complexity. The system is synthesized using 0.18 \(\upmu \)m, and experimental verification using Field-Programmable Gate Array (FPGA) based on Sleep-EDF database. An overall accuracy (ACC) of 79.1% is achieved, which a highest ACC of 86.3% has been measured with specified patient.

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Acknowledgements

This work is supported in part by National Natural Science Foundation of China through grant 61674095, and Thousand Youth Talents Plan.

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Correspondence to Milin Zhang .

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Liao, Y., Zhang, M., Wang, Z., Xie, X. (2019). Design and FPGA Implementation of an High Efficient XGBoost Based Sleep Staging Algorithm Using Single Channel EEG. In: Sun, F., Liu, H., Hu, D. (eds) Cognitive Systems and Signal Processing. ICCSIP 2018. Communications in Computer and Information Science, vol 1005. Springer, Singapore. https://doi.org/10.1007/978-981-13-7983-3_26

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  • DOI: https://doi.org/10.1007/978-981-13-7983-3_26

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-13-7982-6

  • Online ISBN: 978-981-13-7983-3

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