Heterogeneous Integration of Chip-to-Chip Stacks

  • John H. LauEmail author


As pointed out by Intel (Polka et al. in Intel Technol J 11:197–206 (2007), [1]) sometimes ago that the holy grail to address the memory bandwidth challenge for tera-scale computing is to have 3D chip-to-chip and face-to-face stacked MCP (multi-chip packaging), Fig. 9.1. The top chip is a memory and the bottom chip is a logic or CPU (central processing unit). In this chapter, two examples of heterogeneous integration of chip-to-chip and face-to-face are presented. One is with TSVs in the bottom chip to let go the signals, powers, and grounds and the other is without TSVs but with solder bumps on the larger chip.


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© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.ASM Pacific TechnologyHong KongHong Kong

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