LEADER: Leakage Currents Estimation Technique for Aging Degradation Aware 16 nm CMOS Circuits

  • Zia AbbasEmail author
  • Andleeb Zahra
  • Mauro Olivieri
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 892)


Fast-computable and accurate leakage models for state of the art CMOS digital standard cells is one of the most critical issues in present and future nano-scale technology nodes. It is further interesting if such model can calculate leakage currents not only at initial circuit life but also over the years based on Bias Temperature Instability (BTI) aging mechanism, which increases the threshold voltage over the years – thus mitigating leakage – but in turn degrades circuit speed. A reliable quantification of such aging-induced leakage mitigation opens the way to effective trade-off techniques for compensating speed degradation while maintaining leakage within specification bounds. The presented logic level leakage characterization and estimation technique, currently implemented as VHDL packages, shows more than 103 speed-ups over HSPICE circuit simulation and exhibits less than 1% error over HSPICE. We report BTI aging aware leakage current estimation for ten years at 25 °C and 90 °C in 16 nm CMOS technology, and we analyze how such leakage reduction trend can be traded off to improve the degraded circuit speed over time.


NBTI PBTI Leakage current VHDL CMOS 


  1. 1.
    Bhunia, S., Mukhopadhya, S. (eds.): Low-Power Variation-Tolerant Design in Nanometer Silicon. Springer, New York (2011). Scholar
  2. 2.
    International Technology Roadmap for Semiconductors. International SEMATECH, Austin, TX.
  3. 3.
    Chau, R., et al.: Application of high-k gate dielectric and metal gate electrodes to enable silicon and non-silicon logic nanotechnology. Microelectron. Eng. 80, 1–6 (2005)CrossRefGoogle Scholar
  4. 4.
    Abbas, Z., Olivieri, M., Ripp, A.: Yield-driven power-delay-optimal CMOS full adder design complying with automotive product specifications of PVT variations and NBTI degradations. J. Comput. Electron. 15(4), 1424–1439 (2016)CrossRefGoogle Scholar
  5. 5.
    Abbas, Z., Olivieri, M.: Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cell library. Elsevier Microelectron. J. 45(2), 179–195 (2014)CrossRefGoogle Scholar
  6. 6.
    Abbas, Z., Olivieri, M.: Optimal transistor sizing for maximum yield in variation aware standard cell design. Int. J. Circuit Theory Appl. 44, 1400–1424 (2016)CrossRefGoogle Scholar
  7. 7.
    Mukhopadhyay, S., Raychowdhury, A., Roy, K.: Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling. In: Proceedings of IEEE/ACM Design Automation Conference (DAC 2003), pp. 169–174 (2003)Google Scholar
  8. 8.
    Rao, R., Burns, J., Devgan, A., Brown, R.: Efficient techniques for gate leakage estimation. In: Proceedings of International Symposium on Low Power Electronics and Design (ISLPED 2003), pp. 100–103 (2003)Google Scholar
  9. 9.
    Alam, M.A., Mahapatra, S.: A comprehensive model of PMOS NBTI degradation. Microelectron. Reliab. 45(1), 71 (2005)CrossRefGoogle Scholar
  10. 10.
    Schroder, D.K., Babcock, J.A.: Negative bias temperature instability: road to cross in deep submicron silicon semiconductor manufacturing. J. Appl. Phys. 94(1), 1 (2003)CrossRefGoogle Scholar
  11. 11.
    Chin, D., Pan, S., Wu, K.: Geometry effect on CMOS transistor stability under DC gate stress. In: IRPS, pp. 66–70 (1993)Google Scholar
  12. 12.
    Math, G., Benard, G., Ogier, J., Goguenheim, D.: Geometry effects on the NBTI degradation of PMOS transistors. In: Integrated Reliability Workshop Final Report, pp. 60–63 (2008)Google Scholar
  13. 13.
    Tudor, B., et al.: MOSRA: an efficient and versatile MOS aging modeling and reliability analysis solution for 45 nm and below. In: Proceedings of 10th IEEE International Conference on Solid-State Integrated Circuit Technology, pp. 1645–1647 (2010)Google Scholar
  14. 14.
    Abbas, Z., Genua, V., Olivieri, M.: A novel logic level calculation model for leakage currents in digital nano-CMOS circuits. In: Proceedings of IEEE 7th Conference PRIME, pp. 221–224, July 2011Google Scholar
  15. 15.
    Abbas, Z., Mastrandrea, A., Olivieri, M.: A voltage-based leakage current calculation scheme and its application to nanoscale MOSFET and FinFET standard-cell designs. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(12), 2549–2560 (2014)CrossRefGoogle Scholar
  16. 16.
    Dunga, M.W., et al.: BSIM 4.6.1 Mosfet model – user’s manual. Technical reports, EECS Department, University of California, Berkeley (2007)Google Scholar
  17. 17.
    Abbas, Z., Zahra, A., Olivieri, M., Mastrandrea, A.: Geometry scaling impact on leakage currents in FinFET standard cells based on a logic-level leakage estimation technique. In: Anguera, J., Satapathy, S.C., Bhateja, V., Sunitha, K.V.N. (eds.) Microelectronics, Electromagnetics and Telecommunications. LNEE, vol. 471, pp. 283–294. Springer, Singapore (2018). Scholar
  18. 18.
    Predictive Technology Model.
  19. 19.
    HSPICE: MOS Reliability Analysis (MOSRA)Google Scholar
  20. 20.
    Abdollahi, A., Fallah, F., Pedram, M.: Leakage current reduction in CMOS VLSI circuits by input vector control. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 12(2), 140–154 (2004)CrossRefGoogle Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.Center for VLSI and Embedded System Technologies (CVEST)IIIT HyderabadHyderabadIndia
  2. 2.DIETSapienza University of RomeRomeItaly

Personalised recommendations