Advertisement

A Three Input Look-Up-Table Design Based on Memristor-CMOS

  • Junwei Sun
  • Xingtong Zhao
  • Yanfeng Wang
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 952)

Abstract

The logic block of field programmable gate array (FPGA) basic unit is mainly composed of look-up-table (LUT). The conventional LUT using the static random access memory (SRAM), which leads to FPGA almost reach the limitation in term of the density, speed, and configuration overhead. In this paper, a new scheme of improved memristor-based look-up-table (MLUT) is proposed. The MLUT circuit, which is compatible with the mainstream circuit in FPGA. The MLUT effectively solving the limitations of field FPGA and MLUT is more efficient in data transmission than traditional LUT. In addition, the proposed circuit can achieve any combination logic function in MLUT by specific configuration. As a case study, a three-input LUT circuit based on memristor is designed and the correctness of the results is simulated in PSPICE software. The MLUT can replace traditional SRAM-based LUTs and further improve FPGA performance.

Keywords

Memristor Look-Up-Table (LUT) Field programmable gate array (FPGA) 

Notes

Acknowledgment

The work is supported by the State Key Program of National Natural Science of China (Grant No. 61632002), the National Key R&D Program of China for International S&T Cooperation Projects (No. 2017YFE0103900), the National Natural Science of China (Grant Nos. 61603348, 61775198, 61603347, 61572446, 61472372), Science and Technology Innovation Talents Henan Province (Grant No. 174200510012), Research Program of Henan Province (Grant Nos. 172102210066, 17A120005, 182102210160), Youth Talent Lifting Project of Henan Province and the Science Foundation of for Doctorate Research of Zhengzhou University of Light Industry (Grant No. 2014BSJJ044).

References

  1. 1.
    Chua, L.O.: Memristor-the missing circuit element. IEEE Trans. Circuit Theory 18(5), 507–519 (1971)CrossRefGoogle Scholar
  2. 2.
    Strukov, D.B., Snider, G.S., Stewart, D.R., Williams, R.S.: The missing memristor found. Nature 453(7191), 80 (2008)CrossRefGoogle Scholar
  3. 3.
    Tanachutiwat, S., Liu, M., Wang, W.: FPGA based on integration of CMOS and RRAM. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 19(11), 2023–2032 (2011)CrossRefGoogle Scholar
  4. 4.
    Zidan, M.A., Omran, H., Sultan, A., Fahmy, H.A., Salama, K.N.: Compensated readout for high-density MOS-gated memristor crossbar array. IEEE Trans. Nanotechnol. 14(1), 3–6 (2015)CrossRefGoogle Scholar
  5. 5.
    Mohammad, B., Homouz, D., Elgabra, H.: Robust hybrid memristor-CMOS memory: Modeling and design. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 21(11), 2069–2079 (2013)CrossRefGoogle Scholar
  6. 6.
    DeHon, A.: Reconfigurable architectures for general-purpose computing. Ph.D., dissertation, MIT, December 1996Google Scholar
  7. 7.
    Xu, C., Dong, X., Jouppi, N.P., Xie, Y.: Design implications of memristor-based RRAM cross-point structures. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1–6. IEEE Press, New York (2011)Google Scholar
  8. 8.
    Borghetti, J., Snider, G.S., Kuekes, P.J., Yang, J.J., Stewart, D.R., Williams, R.S.: ‘Memristive’ switches enable ‘stateful’ logic operations via material implication. Nature 464(7290), 873 (2010)CrossRefGoogle Scholar
  9. 9.
    Monmasson, E., Cirstea, M.N.: FPGA design methodology for industrial control systems—a review. IEEE Trans. Ind. Electron. 54(4), 1824–1842 (2007)CrossRefGoogle Scholar
  10. 10.
    Yang, J.J., Pickett, M.D., Li, X., Ohlberg, D.A., Stewart, D.R., Williams, R.S.: Memristive switching mechanism for metal/oxide/metal nanodevices. Nat. Nanotechnol. 3(7), 429 (2008)CrossRefGoogle Scholar
  11. 11.
    Snider, G. S.: Architecture, methods for computing with reconfigurable resistor crossbar. U.S. Patent 7,203,789 (2007)Google Scholar
  12. 12.
    Bourdeauducq, S.: Time to digital converter core for spartan 6 FPGAs (2011)Google Scholar
  13. 13.
    Kumar, T.N., Almurib, H.A.F., Lombardi, F.: A novel design of a memristor-based look-up table (LUT) for FPGA. In: 2014 IEEE Asia Pacific Conference on Circuits and Systems, pp. 703–706. IEEE Press, New York (2014)Google Scholar
  14. 14.
    Cong, J., Xiao, B.: mrFPGA: a novel FPGA scheme with memristor-based reconfiguration. In: 2011 IEEE/ACM International Symposium on Nanoscale Architectures, pp. 1–8. IEEE Press, New York (2011)Google Scholar
  15. 15.
    Ahmed, E., Rose, J.: The effect of LUT and cluster size on deep-submicron FPGA performance and density. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 12(3), 288–298 (2004)CrossRefGoogle Scholar
  16. 16.
    Dong, C., Chen, D., Haruehanroengra, S., Wang, W.: 3-D nFPGA: a reconfigurable architecture for 3-D CMOS/nanomaterial hybrid digital circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 54(11), 2489–2501 (2007)CrossRefGoogle Scholar
  17. 17.
    Kuon, I., Rose, J.: Area and delay trade-offs in the circuit and architecture design of FPGAs. In: Proceedings of International Symposium on Field Program Gate Arrays, Monterey, CA, USA (2008)Google Scholar
  18. 18.
    Bruchon, N., Torres, L., Sassatelli, G., Cambon, G.: Magnetic tunnelling junction based FPGA. In: Proceedings of the 2006 ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, pp. 123–130. ACM, New York (2006)Google Scholar
  19. 19.
    Canis, A., Choi, J., Aldham, M., Zhang V.: LegUp: high-level synthesis for FPGA-based processor/accelerator systems. In: Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 33–36. ACM (2011)Google Scholar
  20. 20.
    Gokhale, M., Stone, J., Arnold, J., Kalinowski, M.: Stream-oriented FPGA computing in the streams-c high level language. In: 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 49–56. IEEE Press, New York (2000)Google Scholar
  21. 21.
    Biolek, Z., Biolek, D., Biolkova, V.: SPICE model of memristor with nonlinear dopant drift. Radioengineering 18(2), 210–214 (2009)Google Scholar
  22. 22.
    Qi, A.X., Zhang, C.L., Wang, G.Y.: Memristor oscillators and its FPGA implementation. Adv. Mater. Res. 383, 6992–6997 (2012)Google Scholar
  23. 23.
    Wang, X., Chen, Y.: Spintronic memristor devices and application. In: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 667–672. European Design and Automation Association (2010)Google Scholar
  24. 24.
    Homouz, D., Abid, Z., Mohammad, B.: Memristors for digital, memory and nermorphic circuits. In: 25th International Conference on Microelectronics (ICM), pp. 1–4. IEEE, Beirut (2014)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.Henan Key Lab of Information-Based Electrical AppliancesZhengzhou University of Light IndustryZhengzhouChina
  2. 2.School of Electrical and Information EngineeringZhengzhou University of Light IndustryZhengzhouChina

Personalised recommendations