FPGA Performance Optimization Plan for High Power Conversion

Abstract

One of the major part of any power converter system is a blistering implementation of PWM algorithm for high power conversion. It must fulfil both requirements of power converter hardware topology and computing power necessary for control algorithm implementation. The emergence of multi-million-gate FPGAs with large on-chip RAMs and a processor cores sets a new trend in the design of FPGAs which are exceedingly used to generate the PWM in the area of power electronics. Of late, more and more large complex designs are getting realized using FPGAs, because of less NRE cost and shorter development time. The share of Programmable Logic Devices (PLD), especially FPGAs, in the semiconductor logic market is tremendously growing year-on-year. This calls for an increased controllability of designs, in terms of meeting both area and timing performance, to really derive the perceived benefits. The recent strides in FPGA technology favour the realization of large high-speed designs, which were only possible in an ASIC, in FPGA now. However the routing delay being still unpredictable and the pronounced nature of routing delay over logic delay, in today’s FPGAs impedes the goal of early timing convergence. This paper introduces the few techniques for controlling the design area/time right from architecture stage and the technique can adopt for any FPGA based design applications including the high power conversion. This paper also describes the trade off between Area, speed and power of the optimization techniques.