Abstract
Today, in the modernized digital scenario, speed and area are the crucial design parameters in any digital system design. Most of the DSP applications such as FIR and IIR filters demand high speed adders and multipliers for its arithmetic operations. The structural adders, truncated multipliers, delay elements used in FIR filter implementation consume more area, delay and power. So, in this work by using efficient adders and compressed multipliers, different MAC units are designed and these MAC units are placed in FIR filter architecture to identify the best one structures of FIR filter by evaluating its performance with respect to slices, LUT’s, and combinational delay. The coding is not in Verilog HDL and Simulation is carried by Modelsim 6.3 g. Finally, the design is implemented with Xilinx ISE 12.2 software on Spartan 3E kit.
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Udaya Kumar, N., Subbalakshmi, U., Surya Priya, B., Bala Sindhuri, K. (2018). VLSI Implementation of FIR Filter Using Different Addition and Multiplication Techniques. In: Zelinka, I., Senkerik, R., Panda, G., Lekshmi Kanthan, P. (eds) Soft Computing Systems. ICSCS 2018. Communications in Computer and Information Science, vol 837. Springer, Singapore. https://doi.org/10.1007/978-981-13-1936-5_51
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DOI: https://doi.org/10.1007/978-981-13-1936-5_51
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