Abstract
Due to the advancement in technology, the designing the high-speed frequency multiplier plays the vital role. In this paper, the high speed, the high-reliability frequency multiplier is proposed. By employing an overlap canceller in edge combiner, the high speed highly reliable structure is achieved. The delay locked loop (DLL) has been used to generate a wide range of frequency and high-frequency range by applying logical effort, a proposed frequency minimize a delay which leads to deterministic jitter. In proposing the high speed, high-reliability edge combiner frequency multiplier for silicon on chip process technology is fabricated till 0.13 µm and the output is in the range of 100 MHz–3.3 GHz. Here the power consumption is achieved as 2.9 µw/MHz.
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Pichamuthu, R., Periasamy, P. (2019). High Speed, High-Reliability Edge Combiner Frequency Multiplier for Silicon on Chip. In: Panda, G., Satapathy, S., Biswal, B., Bansal, R. (eds) Microelectronics, Electromagnetics and Telecommunications. Lecture Notes in Electrical Engineering, vol 521. Springer, Singapore. https://doi.org/10.1007/978-981-13-1906-8_32
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DOI: https://doi.org/10.1007/978-981-13-1906-8_32
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