Analytical Investigation of Tunneling Current in Nano-MOSFET Using BSIM4 Model for Low Power VLSI Applications

Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 836)


In this paper, tunneling current in nanoscale MOSFET is analytically investigated using BSIM4 model for very low power VLSI applications. Simulation is carried out for low and high electric fields separately, and appropriate mathematical equations are formulated for that purpose by modifying the existing model proposed by Hu. Effect of dielectric thickness and internally generated electrical parameter variations are measured on tunneling current. Diode-like behavior under the application of high field speaks about the magnitude of critical field where thermionic current starts to dominate. Results are critically important for non-volatile memory applications.


Tunneling current Dielectric thickness Flatband voltage Auxiliary voltage Nano MOSFET Critical electric field 


  1. 1.
    ITRS Roadmap (2007)Google Scholar
  2. 2.
    Lai, P.T., Jingping, X., Liu, B.Y., Xu, Z.: New observation and improvement in GIDL of N-MOSFET’s with various kinds of gate oxides under hot-carrier stress. In: IEEE International Conference on Semiconductor Electronics (1996)Google Scholar
  3. 3.
    Chang, L., Yang, K.J., Yeo, Y.C., Polishchuk, I., King, T.J., Hu, C.: Direct-tunneling gate leakage current in double-gate and ultrathin body MOSFETs. IEEE Trans. Electron Devices 49(12), 2288–2295 (2002)CrossRefGoogle Scholar
  4. 4.
    Lee, W.C., Hu, C.: Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling. IEEE Trans. Electron Devices 48(7), 1366–1373 (2001)CrossRefGoogle Scholar
  5. 5.
    Cassan, E., Dollfus, P., Galdin, S., Hesto, P.: Calculation of direct tunneling gate current through ultra-thin oxide and oxide/nitride stacks in MOSFETs and H-MOSFETs. Microelectron. Reliab. 40(4–5), 585–588 (2000)CrossRefGoogle Scholar
  6. 6.
    Chaves, F.A., Jimenez, D., Sune, J.: Explicit model for the gate tunneling current in double-gate MOSFETs. Solid-State Electron. 68, 93–97 (2012)CrossRefGoogle Scholar
  7. 7.
    Wann, H.J., Ko, P.K., Hu, C.: Gate-induced band-to-band tunneling leakage current in LDD MOSFETs. In: IEDM-92, pp. 147–150 (1992)Google Scholar
  8. 8.
    Chander, S., Singh, P., Baishya, S.: Optimization of direct tunneling gate leakage current in ultrathin gate oxide FET with high-K dielectrics. Int. J. Recent Dev. Eng. Tech. 1(1), 24–30 (2013)Google Scholar
  9. 9.
    Qing-Qing, W., Jing, C., et al.: Gate-to-body tunneling current model for silicon-on-insulator MOSFETs. Chin. Phys. B 22(10), 108501 (2013)CrossRefGoogle Scholar
  10. 10.
    Gehring, A., Selberherr, S.: Modeling of tunneling current and gate dielectric reliability for nonvolatile memory devices. IEEE Trans. Device Mater. Reliab. 4(3), 306–319 (2004)CrossRefGoogle Scholar
  11. 11.
    Govoreanu, B., Blomme, P., Houdt, J.V., De Meyer, K.: Enhanced tunneling current effect for nonvolatile memory applications. Jpn. J. Appl. Phys. 42(1-4B), 2020–2024 (2003)CrossRefGoogle Scholar
  12. 12.
    Hong, S.H., Jang, J.H., Park, T.J., Jeong, D.S., Kim, M., Hwang, C.S.: Improvement of the current-voltage characteristics of a tunneling dielectric by adopting a Si3N4∕SiO2∕Si3N4 multilayer for flash memory application. Appl. Phys. Lett. 87, 152106 (2005)CrossRefGoogle Scholar

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© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.Department of Electronic ScienceA.P.C CollegeKolkataIndia
  2. 2.Department of Electronics and Communication EngineeringRCC Institute of Information TechnologyKolkataIndia

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