Analytical Investigation of Tunneling Current in Nano-MOSFET Using BSIM4 Model for Low Power VLSI Applications
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In this paper, tunneling current in nanoscale MOSFET is analytically investigated using BSIM4 model for very low power VLSI applications. Simulation is carried out for low and high electric fields separately, and appropriate mathematical equations are formulated for that purpose by modifying the existing model proposed by Hu. Effect of dielectric thickness and internally generated electrical parameter variations are measured on tunneling current. Diode-like behavior under the application of high field speaks about the magnitude of critical field where thermionic current starts to dominate. Results are critically important for non-volatile memory applications.
KeywordsTunneling current Dielectric thickness Flatband voltage Auxiliary voltage Nano MOSFET Critical electric field
- 1.ITRS Roadmap (2007)Google Scholar
- 2.Lai, P.T., Jingping, X., Liu, B.Y., Xu, Z.: New observation and improvement in GIDL of N-MOSFET’s with various kinds of gate oxides under hot-carrier stress. In: IEEE International Conference on Semiconductor Electronics (1996)Google Scholar
- 7.Wann, H.J., Ko, P.K., Hu, C.: Gate-induced band-to-band tunneling leakage current in LDD MOSFETs. In: IEDM-92, pp. 147–150 (1992)Google Scholar
- 8.Chander, S., Singh, P., Baishya, S.: Optimization of direct tunneling gate leakage current in ultrathin gate oxide FET with high-K dielectrics. Int. J. Recent Dev. Eng. Tech. 1(1), 24–30 (2013)Google Scholar